Nonvolatile flash-EEPROM memory array with source control transi

Details Nonvolatile flash-EEPROM memory array with source control transi Nonvolatile flash-EEPROM memory array with source control transi

1994-03-15

1996-04-16

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular connection

36518512, 36518527, 36523006, G11C 1134

Patent

active

055089569

ABSTRACT:
To reduce the number of depleted cells and the errors caused thereby, the memory array includes groups of control transistors corresponding to groups of memory cells. The control transistors of each group are NMOS transistors having the drain terminal connected to a control line. Each of the control transistors corresponds to a row portion of the memory array. Each control transistor has a control gate connected to a respective word line and a source region connected by a respective source line to the source regions of the memory cells in the same row and group.

REFERENCES:
patent: 4949309 (1990-08-01), Rao
patent: 4958321 (1990-09-01), Chang
patent: 4972371 (1990-11-01), Komori et al.
patent: 5016215 (1991-05-01), Tigelaar
patent: 5301150 (1994-04-01), Sullivan et al.
patent: 5317179 (1994-05-01), Chen

Affiliated with

Also associated with

Rating

Nonvolatile flash-EEPROM memory array with source control transi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile flash-EEPROM memory array with source control transi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile flash-EEPROM memory array with source control transi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-330691