Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-10-24
2004-08-17
Thompson, Craig A. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S773000
Reexamination Certificate
active
06777813
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to improved fill patterns for semiconductor devices, and more particularly to geometrically simple arrays of fill patterns interspersed among conductive elements to promote the formation of an insulating planarization layer.
The deposition of the numerous layers is one of the key steps in the fabrication of semiconductor devices, where typically alternating patterns of conductive and nonconductive materials are topographically formed on a semiconductor substrate. In a typical photolithographic process, a patterned reticle is employed to provide masking of selected sections of a resist layer on both the semiconductor substrate and subsequent layers, repeated through numerous steps to build a three-dimensional network of connectors. However, the addition of multiple layers causes the topographic projection to become more and more nonplanar; these surface undulations can lead to a loss of resolution in the lithographic masking process.
It is therefore highly desirable from a process and quality control perspective to have as little surface undulation as possible on the built-up semiconductor device. One way to minimize the surface undulation is to planarize each exposed surface with one or more insulative layers using known procedures, such as spin-on glass (SOG) or chemical vapor deposition (CVD) methods. One commonly used material in this CVD process is tetraethylorthosilicate (TEOS). When either of these approaches are used to deposit a layer over large tracts of non built-up area, they tend to produce tapered layer thickness variations near the topographic regions in a manner similar to that of a meniscus formed near a container wall due to surface tension in a liquid. To achieve the desired level of planarization, it is precisely this conformal behavior, prevalent in wide-open areas, that substrate designers have been trying to avoid. Similarly, when spacing widths between the rigid upstanding structures varies, the aforementioned layer fill techniques are less than wholly effective at achieving the desired planarization, as spaces of varying size permit disparate amounts of SOG or TEOS to flow into them, and at different rates.
Additional methods have been employed to improve the planarity of insulative layers. One well-known approach involves the placement of “dummy” or fill patterns in between the topographic conductive elements to reduce the incidence of conformal dips in the insulative layer. The presence of these fill patterns which, by interrupting otherwise large tracts of unsupported fill area, subdivide and create smaller valley- or grid-like regions for SOG or TEOS layers to fill. However, the addition of fill patterns adds complexity, as additional steps must be included to ensure their mechanical and electrical compatibility. For example, since many fill patterns are metal (often deposited simultaneously with the conductive element steps), they can be a source of unwanted conductivity or capacitance. Similarly, a lack of uniformity of spacing between the patterns making up the fill pattern array hampers the even distribution of the layers. The relatively non-uniform spacing between adjacent topographic structures also militates against lower processing costs, where these considerations dictate that fill patterns and the arrays made therefrom be as simple as possible. The cost of depositing customized, non-uniform fill patterns can have a significant impact on fabrication cost; on the other hand, improper attention to a grid or valley layout between fill patterns can lead to spaces that, if inclusive of long straight paths and high throughflow intersections, will exhibit uneven planarization layer flow, and subsequent undulated layer deposition. Accordingly, fill pattern size and spacing become critical design considerations to the person responsible for the circuit layout.
Accordingly, the need exists for devices in which fill patterns can be consistently and substantially planar across the entire region of the upper surface of the semiconductor device to provide inexpensive, compact and reliable structures.
SUMMARY OF THE INVENTION
The present invention satisfies the aforementioned need by providing a planarized semiconductor device and a system which utilizes a reticle configuration that promotes the formation of a planarized landscape on the surface of a semiconductor device. The various layers, regions, and structures of the embodiments of the device according to the present invention may be formed by utilizing conventional semiconductor device fabrication techniques. The selection of these specific techniques may vary from application to application and, with the exception of the fabrication steps outlined herein, is not the subject of the present invention.
According to an aspect of the present invention, a method of fabricating a semiconductor device is disclosed, where the steps include: providing a generally planar semiconductor wafer substrate made up of substantially orthogonal first and second in-plane dimensions; defining a topographic layer of conductive lead line material such that it comprises at least first and second sides that extend coplanar with the wafer substrate; depositing one or more topographic layers of conductive lead line material on the substrate; depositing a plurality of topographic fill patterns adjacent either the conductive lead line material or another fill pattern such that spaces defined between the topographic structures possess substantially equal width as any other space; arranging the topographic fill patterns and the topographic layers of conductive lead line material so that a grid defined by a plurality of crossings of the spaces contains no linear dimension longer than the longest dimension of any one of the topographic fill patterns, and that no intersection defined by any of the plurality of crossings includes uninterrupted linear dimensions. An additional step includes depositing a planarization layer over the substrate such that it fills up the grid pattern, laterally surrounding the topographic structures of conductive lead line material and fill patterns.
Optionally, the step of depositing the insulative layer includes depositing either a layer of spin-on glass or TEOS. In addition, the deposition of the insulative layer produces a top surface substantially co-planar with a top surface of the layers of conductive lead line material and the fill patterns. An additional step may include defining an array comprising at least one of the fill patterns and conductive lead line layers such that no portion of any of the fill patterns overhang the array boundary. The array can be thought of as containing numerous topographic structures repeated in a fairly regular geometric pattern such that it takes on a relatively uniform appearance. One way to achieve a regular geometric pattern is to have the periphery of the array be mostly bounded by the straight-edged sides of the fill patterns.
According to another aspect of the present invention, a semiconductor is disclosed. The semiconductor includes a substantially planar substrate with first and second topographic patterns, or structures, defined by active lead lines and dummy fills (both also referred to as peaks), respectively deposited on the substrate. A repeating array, which itself includes a substantially planar grid comprising a plurality of interconnected valleys circumscribing the first and second topographic patterns, is disposed over the substrate, and is configured such that the array periphery is substantially bounded by straight edges of the dummy fills, active lead lines, or combination of both. Furthermore, no portion of any of the dummy fills extends laterally beyond the periphery. Within the grid, the longest linear dimension of each of the valleys is no longer than the longest lateral dimension of any of the dummy fills, and no intersection defined by a crossing between any two valleys includes uninterrupted linear dimensions. In the alternate, a plurality of first and second topograph
Ireland Philip J.
Juengling Werner
Dinsmore & Shohl
Micro)n Technology, Inc.
Thompson Craig A.
Vesperman William
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