Preconditioning integrated circuit for integrated circuit...

Details Preconditioning integrated circuit for integrated circuit... Preconditioning integrated circuit for integrated circuit...

2001-11-08

2004-06-08

Pert, Evan (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06747469

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of integrated circuit technology, and in particular to the testing of integrated circuits.
2. Description of Related Art
The testing of integrated circuits, particularly at high frequency, is becoming increasingly more complex, and therefore more costly. Test equipment must be continually upgraded and enhanced to include capabilities for testing devices that typically include the latest state-of-the-art technology.
FIG. 1
illustrates an example test system
100
comprising automated test equipment (ATE)
110
that is coupled to a device-under-test (DUT)
150
via a probe card
140
. The ATE
110
typically includes a set of core test components
120
, and special purpose test modules
130
. In the example of
FIG. 1
, the system
100
is configured to enable testing of high-speed multimedia devices, using, for example, special purpose audio and video modules in the set of test modules
130
. If the system
100
is used to test communications devices, the set of test modules
130
may contain, for example, discrete Fourier transform (DFT) modules, and other modules particular to communications devices. As the technologies used in the development of new devices
150
are advanced, the test modules
130
must be upgraded to keep pace with these advancements.
One of the particular problems associated with the testing of high-speed devices is the communication of signals to and from the device-under-test
150
, particularly in the case of wafer-level testing. Long lead lines
111
from the test equipment
110
to the device-under-test
150
add capacitive and inductive loads to the driving signals. This additional load introduces a delay or mis-shaping of signals to and from the device-under-test
150
. In many instances, certain tests cannot be performed ‘at device speed’, due to the distortions introduced by the long lead lines
111
. Often, because the test system
100
is limited by the available test modules
130
, the length of the leads
111
, and other factors, tests are designed to correspond to the capabilities of the test system
100
, rather than to the capabilities of the device-under-test
150
. Additionally, because both the length and placement of the lines
111
affect the high-frequency characteristics of the lead lines
111
, substantial time is often consumed to experiment with the mechanical setup. During testing, substantial time is often consumed in determining whether an observed anomalous behavior is caused by a problem in the device-under-test
150
, or a problem in the test setup.
EP 0755071 teaches an alternative technique where the test system
100
is replaced by a special purpose integrated circuit that is configured to directly contact bonding pads on the device-under-test
150
, as illustrated in FIG.
2
. This special purpose integrated circuit
201
includes “solder-bump” contacts
205
that are configured to contact corresponding contact pads
240
on the device-under-test
150
.
As taught in the referenced patent, the probe card
140
is configured to effect the testing of the device-under-test
150
, using test circuitry
202
in the integrated circuit
201
, thereby eliminating the need for the test equipment
110
of FIG.
1
. In accordance with this referenced patent, the special purpose integrated circuit
201
receives power
203
from an external source to power the test circuitry
202
, and includes a light emitting diode (LED) that indicates whether the device-under-test
150
is defective. Because the test circuitry
202
is designed to be a stand-alone device that is capable of determining whether or not the device-under-test
150
is defective, without reliance upon the automatic test equipment
110
of
FIG. 1
, the design of the test circuitry
202
can be expected to be a complex and time consuming process. Additionally, because the test circuitry
202
is designed to test a particular device
150
, the design and fabrication costs for the integrated circuit
201
cannot be allocated among a variety of devices.
BRIEF SUMMARY OF THE INVENTION
It is an object of this invention to provide a test system that minimizes the adverse affects caused by long lead lines between automated test equipment and a device-under-test. It is a further object of this invention to provide a test architecture that facilitates the testing of a variety of devices. It is a further object of this invention to provide a preconditioning integrated circuit that is configurable for use in the testing of a variety of devices.
These objects and others are achieved by a test system that includes a preconditioning integrated circuit that is coupled between automatic test equipment (ATE) and a device-under-test (DUT). The preconditioning integrated circuit is configured to precondition signals that are communicated to and from the device-under-test, and particularly, to precondition high-frequency signals so as to avoid the adverse affects caused by long lead lines between the automated test equipment and the device-under-test. The preconditioning integrated circuit is designed to provide direct contact with the device-under-test, thereby providing very short lead lines to the device-under-test. High-frequency signals that are communicated to the device-under-test are generated, or reformed, at the preconditioning integrated circuit, based on control signals, or other test signals, from the automated test equipment. High-frequency, or time-critical, signals that are received from the device-under-test are processed and/or reformed by the preconditioning integrated circuit, for subsequent transmission to the automated test equipment.


REFERENCES:
patent: 5323107 (1994-06-01), D'Souza
patent: 5903164 (1999-05-01), Kline
patent: 6075373 (2000-06-01), Iino
patent: 6169410 (2001-01-01), Grace et al.
patent: 6486693 (2002-11-01), Conner et al.
patent: 0 755 071 (1996-07-01), None
patent: WO 96 17378 (1996-06-01), None
IEEE 100 (The Authoritative Dictionary of IEEE Standards Terms), 7th Edition, Published by Standards Information Network IEEE Press, 2000, p. 570.*
Copending U.S. patent application Ser. No. 10/005,689, Rutten, filed Nov. 8, 2001, Rutten “Chip-Mounted Contact Springs”.
“Introducing WOW Technology”, http://www.formfactor.com/about/wow/wow_pg2.html.
“Introducing WOW Technology”, http://www.formfactor.com/about/wow/wow_pg5.html.
“Focus on FormFactor”, The Final Test Report, vol. 12, No. 09, Sep. 2001, Ikonix Corp. P.O. Box 1938, Lafayette, CA 94549-1938.
“Flip-Chip Bonding on 6-um Pitch using Thin-Film Microspring Technology”, Donald L. Smith et al., Xerox Palo Alto Research Center, Proceedings, 48thElectronic Components and Technology Conference, IEEE, May 1998.

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