High voltage generation circuit

Details High voltage generation circuit High voltage generation circuit

2001-06-29

2004-08-31

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S539000

Reexamination Certificate

active

06784723

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from Korean Application, entitled “High Voltage Generation Circuit” Application No. 2000-36944 and filed on Jun. 30, 2000 and incorporates by reference its disclosure for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-voltage generation circuit and in particular, to a high-voltage generation circuit which is capable of sequentially enabling a high-voltage pump to obtain high-precision pumping, to thereby generate a stabilized high voltage.
2. Description of the Prior Art
In a semiconductor device using an external power supply, a high-voltage generation circuit is widely used. Because the high-voltage generation circuit generates a voltage higher than the external power supply of the threshold voltage of a transistor, the circuit can compensate for a loss of threshold voltage.
FIG. 1
is a schematic block diagram of a conventional high-voltage generation circuit. As shown in this FIG., a conventional high-voltage generation circuit includes a high-voltage level detection unit
1
, a high-voltage pump control unit
2
, an oscillator
3
, a plurality of high-voltage pumps
41
,
42
-
4
N, and a high-voltage clamping unit
5
.
The high-voltage level detection unit
1
detects an input of voltage VPP and generates both a detection signal DET to produce a stable voltage of VPP and a clamping active signal CLMP. High-voltage pump control unit
2
generates a high-voltage pump control signal VPPEN in response to detected signal DET from high-voltage level detection unit
1
.
In response to the high-voltage pump control signal VPPEN, oscillator
3
generates both a pulse signal OSC for driving the plurality of high-voltage pumps
41
,
42
-
4
N, and a pump active signal PACT for controlling pumps
41
,
42
-
4
N. Pumps
41
,
42
-
4
N then pump to obtain a high voltage level under the control of the pulse signal OSC and the pump active signal PACT. High-voltage clamping unit
5
operates to clamp the level of high voltage based on the clamping active signal CLMP from high-voltage level detection unit
1
.
FIG. 2
is a detailed block diagram of one of the plurality of high-voltage pumps
41
,
42
-N shown in FIG.
1
. In
FIG. 2
, a high-voltage pump
41
includes a first NAND gate ND
1
, a first through a fourth NOR gate NOR
1
to NOR
4
, a first through a fourth precharge capacitor C
1
to C
4
, a first and a second NMOS transistor NM
1
and NM
2
, and a first and a second PMOS transistor PM
1
and PM
2
. Specifically, the first NAND gate ND
1
performs a NAND operation on an inverted pump active signal PACT signal from first inverter INV
1
and the pulse signal OSC.
First NOR gate NOR
1
performs an OR operation on the output of first NAND gate ND
1
and the outputs consecutively processed through second inverter INV
2
. Second NOR gate NOR
2
and a fourth inverter INV
4
outputs the resultant data signal to a third inverter INV
3
through NOR
1
. Second NOR gate NOR
2
performs an OR operation on the output of third inverter INV
3
and the output of second inverter INV
2
, and outputs the resultant data signal to fourth inverter INV
4
.
Third NOR gate NOR
3
performs an OR operation on the output of third inverter INV
3
and the output of a fifth inverter INV
5
. INV
5
operates to invert the output of the third inverter INV
3
, and the resultant data signal is output as first pump driving signal G
1
. Fourth NOR gate NOR
4
performs an OR operation on the output of fourth inverter INV
4
and the output of a sixth inverter INV
6
. INV
6
functions to invert the output of fourth inverter INV
4
, and the resultant data signal is output as a second pump driving signal G
2
.
A first precharge capacitor C
1
precharges the high-voltage pump based on first pump driving signal G
1
from third NOR gate NOR
3
. A second precharge capacitor C
2
precharges the high-voltage pump based on second pump driving signal G
2
from fourth NOR gate NOR
4
. A third capacitor C
3
pumps the high voltage based on output R
1
of third inverter INV
3
, and a fourth capacitor C
4
pump high voltage based on the output R
2
of fourth inverter INV
4
.
A first NMOS transistor NM
1
is configured to enable the output of first precharge capacitor C
1
to precharge the high-voltage pump by using an external supply voltage VEXT. A second NMOS transistor NM
2
, is configured to enable the output of second precharge capacitor C
2
to precharge the high-voltage pump by using the external supply voltage VEXT.
A first PMOS transistor PM
1
, having a gate coupled to a precharged node of second NMOS transistor NM
2
functions to transmit the high voltage to a Vpp node. A second PMOS transistor PM
2
, having a gate coupled to a precharged node of first NMOS transistor NM
1
operates to transmit the high voltage. In one embodiment, PM
1
and PM
2
transmit the high voltage at different times, according to, for example, the signal OSC.
A detailed explanation of the operation of a conventional high-voltage generation circuit follows. First, the level of high voltage is reduced, over time, to a non-conforming level. High-voltage level detection unit
1
outputs a detected signal DET smaller (i.e., less) than the internal power supply VDD, which is the core power supply of the DRAM.
Accordingly, high-voltage pump control unit
2
outputs a high-voltage pump control signal VPPEN at a high level (e.g., VDD). Accordingly, oscillator
3
outputs pump active signal PACT at a low level (i.e., a low logic level such as Vss) and pulse signal OSC at a periodic low level.
Each of the plurality of high-voltage pumps-
41
-
4
N function to simultaneously perform a voltage pumping operation in response to pump active signal PACT and pulse signal OSC.
FIGS. 3A and 3B
are timing views illustrating the operation of a conventional high-voltage generation circuit. As shown in
FIGS. 3A and 3B
, the high-voltage level (e.g., VPP) is greatly increased each cycle of the pulse signal OSC of oscillator
3
. If the high voltage increases to a certain high level beyond maximum level of voltage, detected signal DET from detection unit
1
initiates high-voltage pump control signal VPPEN logic low, thus disabling the plurality of high-voltage pumps
41
-
4
N to halt charge pumping.
In this case, the high-voltage level is sequentially reduced over time and is quickly dropped down into a conforming or acceptable range of high-voltage levels during an active mode rather than during a standby mode.
As mentioned above, if the high voltage level drops to a level less than a certain level, the procedure discussed above is repeated to recommence the voltage pumping.
Conversely, if high voltage rises to a level higher than a maximum high voltage level, high-voltage level detection unit
1
enables the clamping active signal CLMP to perform the clamping operation, preventing the high-voltage level from rising excessively. The use of high-voltage pumps
41
-
4
N is well-known in the art and therefore, a description of their operation is omitted.
As shown in
FIG. 3B
, the conventional high-voltage generation circuit described above simultaneously activates the plurality of high-voltage pumps
41
-
4
N, and the high-voltage level VPP rises in a chopping wave fashion during one cycle of the pulse signal OSC of oscillator
3
.
At the instant high-voltage pump control signal VPPEN transitions to a logic low, the pulse signal OSC of oscillator
3
transistors to a logic high to allow the plurality of high-voltage pumps
41
-
4
N to be simultaneously activated. As a result, an increase in the high-voltage level is produced.
During an actual pumping operation, after high-voltage level is detected, feedback to the high-voltage pump control signal VPPEN causes a delay, resulting in an increased voltage that exceeds a desired maximum high-voltage level.
Accordingly, the conventional high-voltage generation circuit suffers from the drawback that if the high-voltage level is greatly varied, an excessive level of stress may be applied to the m

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