Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2002-09-10
2004-12-14
Stoner, Kiley (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S180220, C228S234200, C228S248100
Reexamination Certificate
active
06830177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the mounting and connecting of devices and, in particular, to the mounting and connecting of microelectronic units such as chip scale packages (“CSPs”) on printed wiring boards (“PWBs”).
2. Description of the Prior Art
Early methods of mounting and connecting semiconductor chips to PWBs frequently resulted in unreliable connections. Specifically, the early methods provided an electrical connection between a semiconductor chip and a PWB that consisted of a solder joint. Though suitable for environments such as desktop use, such electrical connections proved unreliable in harsh environments that subject the board and chip to vibrations and temperature variations. The vibrations frequently caused fatigue failures in the solder joints. Temperature variations caused connection failures due to the difference in the thermal coefficients of expansion (“TCE”) for the semiconductor chips and the PWB. A material's TCE is the rate at which the material expands or contracts in relation to changes in its temperature. PWBs, for example, frequently have a TCE that is higher than that of the semiconductor chips.
The differences in the TCEs for PWBs and semiconductor chips frequently caused solder joint strains on early chip mounted boards and often interrupted the electrical connections between the semiconductor chips and the PWB. To solve this problem, manufacturers developed improved methods of connecting semiconductor chips to PWBs. For example, manufacturers developed peripheral grid array (“PGA”) chips configured to have leads arranged about the chip's periphery.
As shown in U.S. Pat. No. 4,827,611, No. 5,294,039, and No. 5,317,479, PGA chip design initially incorporated S-shape leads to compensate for the different TCEs for the PGA chip and the PWB. However, the drive to miniaturize semiconductor chip and PWB assemblies soon led to the development of C-shaped leads, because the S-shaped leads left too much space between the surface of the PWB and semiconductor chip. The C-shaped leads reduced the spacing between the surface of the chip and the PWB, and thus provided a mounted chip with a profile lower than a chip equipped with S-shaped leads. When used in external environments, which subjected the mounted assembly to vibration and wide temperature variations, the C-shape retained the lead's ability to compensate for the different TCEs of the chip and the PWB.
Prior to the advent of area grid array (“AGA”) semiconductor chips, the C-shaped and the S-shaped leads proved adequate in dealing with the problem of differing TCEs for PGA semiconductor chips and PWBs. With AGA chips, however, the conductive connecting surface pads of the chip are arranged in a matrix array. Each connecting surface pad in the matrix is electrically coupled to a similar conductive pad located within a reciprocal corresponding matrix on the PWB. The means used to connect the AGA chip to the PWB typically consists of solder joints individually formed into a spherical shape. AGA chips, which employ the typical solder ball joints, are sometimes referred to as ball grid array (“BGA”) chips. Prior art
FIGS. 1 and 2
show the use of such a BGA.
FIG. 1
illustrates an AGA chip
50
having an array of conductive pads
95
.
FIG. 2
illustrates AGA chip
50
connected to a PWB
70
using solder balls
90
, solder joints
55
formed between solder balls
90
and the conductive pads of AGA chip
50
, and solder joints
77
formed between solder balls
90
and the corresponding conductive pads (not shown) of PWB
70
. Solder balls
90
are typically made from conventional solder which, for example, may consist of 63 weight percent tin and 37 weight percent lead, or 10 weight percent tin and 90 weight percent lead, or an equivalent alloy. However, like the original semiconductor solders joints, solder ball joints are not very reliable when AGA chip
50
and PWB
70
are subjected to temperature variations and/or mechanical vibrations. Moreover, once AGA chip
50
is mounted on PWB
70
, accessing a connection point between a single connection pad on AGA chip
50
and a reciprocal conductive pad on PWB
70
is difficult. When the solder ball joint fails, the entire AGA chip
50
must be removed from the PWB
70
in order to effect repairs. While AGA chips have reduced space required to connect the chips to the board, the reliability problems associated with solder joints between semiconductor chips and PWB have continued.
One attempted solution includes the use of solder columns instead of solder ball spheres. The solder columns are typically made of solder alloy having a composition of 10 weight percent tin and 90 weight percent lead. However, solder columns do not provide improved strength or reliability over solder balls. In addition, the high lead content of this solder alloy is highly undesirable because of heavy environmental pressure to avoid introducing additional lead into the environment.
Attempts have been made to use conductive leads to connect an AGA chip to a PWB. For example, U.S. Pat. No. 5,455,390 discloses a method of placing a plurality of conductive connecting leads between the conductive surface pads of the AGA chips and the corresponding connecting surface pads of the PWB. However, this method still results in connection failures because relatively unreliable materials, for example, gold, are used to make the conductive connecting leads.
U.S. Pat. No. 6,000,126 discloses an improved method of interconnecting an AGA chip to a printed wiring board. This method includes orienting a first side of a matrix of a plurality of conductive leads, secured relative to one another in parallel by an insulating carrier, so that the first ends of the leads are aligned with a corresponding matrix of conductive surface pads on an AGA chip. The leads are electrically connected to the corresponding conductive surfaces of the AGA chip. Next, the second side of the matrix of leads is oriented so that the second ends of the leads are aligned with a corresponding matrix of connecting surface pads on a PWB. The leads of the second side of the matrix are electrically connected to the corresponding conductive surface pads of the PWB, thereby establishing an electrical connection between the AGA chip and the PWB. While this method offers substantial advantages over the prior art, implementation remains relatively expensive, and the electronic assemblies that incorporate this method continue to experience interconnection reliability problems when subjected to harsh environmental conditions. In addition, this method is not applicable to modern plastic encapsulated microelectronic (“PEM”) chip scale packages (“CSP”) with fine-pitch (0.8 mm or less) AGA type interconnections involving miniature solder balls (0.5 mm or less) on miniature pads (0.3 mm or less).
SUMMARY OF THE INVENTION
The present invention comprises cost-effectively manufactured, electrically conductive and mechanically compliant micro-leads and a method of utilizing these compliant micro-leads to interconnect an area grid array CSP to a PWB. The preferred method includes orienting a plurality of conductive compliant micro-leads, secured to one another in parallel with tie bars and tooling, to align with a corresponding pattern of conductive pads located along the surface of an area grid array CSP. The compliant micro-leads are electrically connected and mechanically secured to the connecting surfaces of the area grid array CSP. Next, the securing tie bars and tooling are removed. The opposite ends of the conductive compliant micro-leads are then oriented to align with a corresponding pattern of conductive surface pads on a PWB. The opposite end of each compliant micro-lead is then electrically connected and mechanically secured to its corresponding connecting pad located on the surface of the PWB, thereby establishing a compliant electrical connection between the area grid array CSP and the PWB.
The compliant micro-leads of the present invention provide more mechanical c
General Dynamics Information Systems, Inc.
Stoner Kiley
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