Data processing: speech signal processing – linguistics – language – Audio signal bandwidth compression or expansion
Reexamination Certificate
2002-08-12
2004-08-24
To, Doris H. (Department: 2655)
Data processing: speech signal processing, linguistics, language
Audio signal bandwidth compression or expansion
C704S502000
Reexamination Certificate
active
06782368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital signal processing, and in particular to a media processing apparatus that decompresses compressed video data and compressed audio data, and can also compress video data and audio data and perform graphics processing.
2. Description of the Related Art
With the development of compressing/decompressing techniques for digital video data and the improvements in LSI (Large Scale Integration) technology in recent years, various media processing circuits have come to be highly valued. Examples of such are a decoder that decodes (decompresses) compressed video and audio data, an encoder that compresses video and audio data, and a graphics processor that processes graphics.
As one example of conventional techniques, an AV (Audio Visual) decoder decodes video data and audio data compressed according to MPEG (Moving Picture Experts Group) standard. This AV decoder uses two processors, with one processor decoding video data and the other processor decoding audio data.
FIG. 1
shows a representation of the decode processing performed by this AV decoder. In
FIG. 1
, the vertical axis represents time and the horizontal axis represents the respective computational complexity of the video decoding performed by the video processor and the audio decoding performed by the audio processor.
The video processor alternately performs sequential processing for compressed video data in macroblock units and decode processing for the actual video data. The sequential processing part of the video decoding analyzes the header part of a macroblock being processed, and so is hereinafter referred to as “header analysis”. The decode processing decodes the compressed video data in a macroblock, and so is hereinafter referred to as “block decoding”. Of these, header analysis requires judgement of various conditions and has a low computational complexity. Block decoding decodes the variable-length codes in an MPEG stream using the various kinds of data produced by the header analysis, and also performs IQ (Inverse Quantization) and IDCT (Inverse Discrete Cosine Transform) processing in block units. This means that the block decoding has a high computational complexity.
The audio processor alternately performs sequential processing for compressed audio data and decoding processing for the actual audio data.
The above technique has the following problems.
The first problem is the cost of manufacturing this AV decoder. In particular, the video processor needs to be a high performance processor that can perform real-time processing on a large amount of video data. This means that a processor with a high clock speed must be used. Such processors are expensive.
When the media processing apparatus described above is used in an AV decoder provided in a digital (satellite) broadcast tuner (called an STB (Set Top Box)) or a DVD (Digital Versatile/Video Disc) player, MPEG streams received on a broadcast wave or read from a disc are inputted. The AV decoder decodes these MPEG streams, and outputs video signals and audio signals to a display and speakers, respectively. This series of processes requires a huge amount of processing. For this reason, there has been increasing demand for a media processing apparatus which can efficiently execute this huge amount of processing.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a media processing apparatus that performs a series of processes composed of the input of stream data that expresses compressed video and compressed audio, decoding of the data, and output of the result, the media processing apparatus having a high performance without operating at a high clock frequency. This reduces the manufacturing cost of the media processing apparatus.
The first object can be achieved by a media processing apparatus that decodes a data stream including compressed audio data and compressed video data to obtain video data and audio data, the media processing apparatus including: a sequential processing unit for performing a header analysis process on the compressed video data and an audio decode process on the compressed audio data, the header analysis process being given priority over the audio decode process and being a header analysis for a predetermined block included in the compressed video data in the data stream, and the audio decode process being a decode process for the compressed audio data; and a routine processing unit for performing a decode process for the compressed video data aside from the header analysis process, the routine processing unit operating in parallel with the sequential processing unit.
With the stated construction, the processing load of the decoding of compressed video data is shared by the sequential processing unit and the routine processing unit, so that the processing load is less than when the entire decode was conventionally handled by a single processor. This raises the overall processing efficiency. The sequential processing unit performs the header analysis process with priority over the audio decode process, so that the decode process of the routine processing unit that is based on the header analysis is performed without delay. This speeds up the overall processing of the media processing apparatus. The audio decode process requires considerably less processing than the decode process for the compressed video data, and is performed by the sequential processing unit in between header analysis processes which also results in higher processing efficiency. Consequently, the media processing apparatus of the present invention achieves a high performance without operating at a high clock frequency, thereby reducing the manufacturing cost of the media processing apparatus.
Here, the sequential processing unit may include a processor and a memory that stores a header analysis thread, an audio decode thread, and a thread switching thread, the processor executing the threads in the memory to realize: a header analysis unit that performs the header analysis process as a result of the processor executing the header analysis thread in the memory; an audio decode unit that performs the audio decode process as a result of the processor executing the audio decode thread in the memory; and a control unit that controls a switching of a thread assigned to the processor so that the header analysis process is given priority over the audio decode process, the control unit being realized by the processor executing the control thread.
With the present construction, the control unit assigns threads to the processor so that the header analysis process is executed with priority. As a result, the media processing apparatus smoothly switches between the header analysis process and the audio decode process and so can process data streams with high efficiency.
Here, the control unit may include: an interrupt detection unit for detecting an occurrence of any of a plurality of interrupts that cause a switching of thread; a state management unit for managing a state of the header analysis unit and a state of the audio decode unit based on a type of detected interrupt, each state being one of an execute state, a wait state, and a ready state; and a switching unit for switching, when the state of the header analysis unit has changed from the wait state to the ready state, a thread assigned to the processor to the header analysis thread.
With the stated construction, the control unit has an interrupt detection unit, a state management unit, and a switching unit. The interrupt detection unit detects interrupts. The state management unit manages changes in the states of the header analysis process and the audio decode process that are caused by interrupts detected by the interrupt detection unit. The switching unit assigns the header analysis thread to the processor when the state of the header analysis unit changes to the ready state. As a result, the control unit is a system that is activated by interrupts, so that there is no need to constantly monitor whic
Fujii Shigeki
Nakatani Shintarou
Matsushita Electric - Industrial Co., Ltd.
Opsasnick Michael
To Doris H.
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