Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2003-06-11
2004-02-03
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185020, C365S185180, C365S200000, C365S201000, C365S189120
Reexamination Certificate
active
06687157
ABSTRACT:
FIELD OF INVENTION
The invention relates generally to methods and circuits for identifying a defective memory cell in an array of memory cells.
BACKGROUND
Conventionally, non-volatile semiconductor memory structures with high levels of integration (e.g., EPROM, EEPROM, flash EPROM, and the like) suffer from high defect rates. A significant percentage of defects common to non-volatile memory produce so-called “leaky” memory cells, which lead to memory misreads, greatly depressing memory yield.
FIG.
1
(
a
) (prior art) depicts a configurable memory cell
100
, including a storage transistor T
1
. Storage transistor T
1
includes a floating gate
115
, a control gate
117
connected to a wordline
120
, a drain terminal
125
connected to a bitline
130
, and a source terminal
135
connected to a ground terminal. During a programming operation, different voltages are applied to wordline
120
and bitline
130
causing electron tunneling from floating gate
115
to drain
125
. This transfer of negative charge from floating gate
115
decreases the threshold voltage of storage transistor T
1
(to a programmed threshold voltage V
THP
). During an erase operation, different voltages are applied to wordline
120
and bitline
130
causing electron tunneling from drain
125
to floating gate
115
, the reverse of the programming process. This transfer of negative charge to floating gate
115
increases the threshold voltage of storage transistor T
1
(to an erased threshold voltage V
THE
).
To read memory cell
100
, a read voltage V
R
is applied to wordline
120
. The threshold voltage V
THP
of a programmed cell is less than the read voltage V
R
, SO transistor T
1
conducts with read voltage V
R
applied to control gate
117
if memory cell
100
is programmed; in contrast, the threshold voltage V
THE
of an erased cell is above the read voltage V
R
, so transistor T
1
does not conduct with read voltage V
R
applied to wordline
120
if memory cell
100
is erased. Whether a given cell conducts with the read voltage applied to the control gate is therefore indicative of the program state of the cell. In the following examples, the programmed state corresponds to a logic-zero state (a “logic zero”) and the erased state corresponds to a logic-one state (a “logic one”).
FIG.
1
(
b
) (prior art) depicts a memory array
150
including N rows and M columns of memory cells
100
. Each row of memory array
150
includes M storage transistors T
1
with their respective control gates connected to one wordline. For example, all M control gates of storage transistors T
1
in a first row are connected to a first wordline WL<1>. Each column of memory array
150
includes N storage transistors T
1
with their respective drain terminals connected to one bitline. For example, all N drain terminals of storage transistors T
1
in a first column are connected to a first bitline BL<1>.
As discussed above in connection with FIG.
1
(
a
), programming and erasing memory cells
100
of memory array
150
includes applying appropriate voltages on the M wordlines and N bitlines. Program and erase voltages are chosen so that all memory cells
100
in memory array
150
exhibit a nominal programmed threshold voltage V
THP
and a nominal erased threshold voltage V
THE
. The nominal values of programmed and erased threshold voltages V
THP
and V
THE
determine the appropriate read voltage V
R
value used during a read operation.
During a read operation, all bitlines are pre-charged to a relatively high voltage representative of a logic one. Then read voltage V
R
is applied to a selected wordline WL<K> while a read-inhibit voltage V
RI
less than the programmed threshold voltage V
THP
is applied to all unselected wordlines (i.e., the control gates of the cells-within memory array
150
not being read). Thus biased, only programmed memory cells on the selected wordline WL<K> will conduct, pulling respective bitlines to a low voltage level representative of a logic zero; and neither programmed nor erased cells on all unselected wordlines conduct.
Memory array
150
can have one or more defective memory cells. A memory cell is “defective” if its electrical characteristics are outside of an acceptable range. For example, a leaky memory cell exhibits a programmed threshold voltage V
THP
that is substantially less than required. If the programmed threshold voltage V
THP
of a given memory cell is below the read-inhibit voltage V
RI
, that memory cell will “leak” when not selected, causing the associated column to read a logic zero regardless of whether a programmed or erased cell is selected.
Modern memory circuits include spare rows or columns of memory cells that can be substituted for respective rows or columns that include defective cells. It can be difficult, however, to precisely locate some types of defects. For example, a leaky memory cell affects an entire column, making it difficult to single out the defective cell. Replacing the defective column solves the problem in many instances; however, redundant rows are preferred for some memory architectures, so it may be important to identify the defective row. Moreover, even in the absence of redundant rows or columns, identifying defective memory cells aids in troubleshooting manufacturing processes. There is therefore a need for circuits and methods for identifying individual defective memory cells.
SUMMARY
The present invention is directed to circuits and methods for identifying defective memory cells in memory arrays. In one embodiment, all the memory cells in an array are programmed to conduct with a conventional read voltage applied and not to conduct with a conventional read-inhibit voltage applied. Any rows that conduct with the read-inhibit voltage applied are termed “leaky,” and are defective. Another read-inhibit voltage lower than the conventional level is selected to cause even leaky cells not to conduct. This test read-inhibit voltage is consecutively applied to each row under test. If one of the rows includes a leaky bit, that bit will conduct with the conventional read-inhibit voltage applied but will not conduct with the test read-inhibit voltage applied. The test flow therefore identifies a row as including a leaky bit when a leak is suppressed by application of the test read-inhibit voltage. A redundant row can be provided to replace a row having a leaky bit.
In one embodiment, a memory array includes a test row and some wordline select logic. During a test operation, the wordline select logic simultaneously applies three wordline voltages, a pair of read-inhibit voltages V
RI1
and V
RI2
and a read voltage V
R
, to wordlines in the memory-cell array. The first wordline voltage V
RI1
is an unusually low read-inhibit voltage of a level selected to insure that even leaky cells will not conduct. The second and third wordline voltages V
RI2
and VR are conventional read-inhibit and read voltages, respectively.
In a test method in accordance with one embodiment, each memory cell is erased (i.e., is configured to exhibit a relatively high erased threshold voltage V
THE
). Each row other than the test row is then programmed (i.e., is configured to exhibit a relatively low programmed threshold voltage V
THP
). The wordline select logic then applies the conventional read voltage V
R
to the wordline of the test row. Being erased, the memory cells in the test row do not conduct. At the same time, the wordline select logic applies the low read-inhibit voltage VRI
1
to the wordline associated with one of the rows under test and applies the conventional read-inhibit voltage V
RI2
to the remaining wordlines.
The read voltage on the test-row wordline is less than the erased threshold voltage, so the memory cells in the test row are biased off and will not conduct. The first read-inhibit voltage is less than the programmed threshold voltage, so low in fact that even leaky cells will not conduct. Thus, the memory cells within the associated row will not conduct even if leaky. Finally, the second read-inhibit voltage will prev
Ahrens Michael G.
Liu Ping-Chen
Miu Kenneth V.
Behiel Arthur J.
Liu Justin
Tran Andrew Q.
Xilinx , Inc.
Young Edel M.
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