Method of forming ferroelectric random access memory cell

Details Method of forming ferroelectric random access memory cell Method of forming ferroelectric random access memory cell

2002-06-11

2004-12-07

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

06828160

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to ferroelectric memory devices, and more particularly to ferroelectric random access memory devices formed with an inverted T-shaped gate stack and methods for making the same.
BACKGROUND OF THE INVENTION
Memory devices including ferroelectric films have attracted attention for their nonvolatile characteristics. Such memory devices are also desirable for high speed reading and writing capabilities that result from their non-destructive read out memory characteristics, which results from storing information as a polarization direction rather than as a charge on a capacitor.
Ferroelectric memory devices may comprise various components. One type of a ferroelectric random access memory (“FeRAM”) has a two transistor, two capacitor configuration similar to a DRAM. Such a device is discussed in greater detail in “Ferroelectric Memory Applications,” J. F. Scott, et al., ULTRASONIC SYMPOSIUM, 299 (1989). Another type of FeRAM is a transistor-cell type—ferroelectric field effect transistor (“FeFET”)—which stores data in ferroelectric gate transistors, and which requires no capacitor structure similar to a DRAM. The latter type of FeRAM provides the advantages over the first type of occupying less surface area and providing non-destructive readout.
Various types of FeFETs may be constructed, each having its own advantages and drawbacks. The various types may include an MFS FET, which comprises a metal layer, a ferroelectric layer, and a semiconductor layer; an MFIS FET, which comprises a metal layer, a ferroelectric layer, an insulator layer, and a semiconductor layer; an MFMS FET, which comprises a metal layer, a ferroelectric layer, a metal layer, and a semiconductor layer; and an MFMIS FET, which comprises a metal layer, a ferroelectric layer, a metal layer, an insulator layer, and a semiconductor layer.
Although FeFET devices possess many desirable characteristics, many problems have been encountered in attempts to fabricate certain types of efficient FeFET devices. For example, it is difficult to form an acceptable crystalline ferroelectric film directly on semiconductor material. Additionally, because of a chemical reaction between ferroelectric and semiconductor materials, it is difficult to have a clean interface between the ferroelectric material and the semiconductor material as ferroelectric material may diffuse into a silicon substrate. Further, there may be a problem retaining an adequate electric charge in the ferroelectric material.
In the past, these problems have been addressed with the MFMIS FET. The MFMIS FET provides a metal layer between the ferroelectric layer and semiconductor layer, thus providing a buffer layer. The composition and past methods of fabricating an MFMIS FET circuit present problems of their own. An MFMIS FET includes an MIS capacitor in series with an MFM capacitor. For efficient low voltage operation of the MFMIS FET, the capacitance ratio between the MFM capacitor and the MIS capacitor cannot be too large. However, because the dielectric constant of ferroelectric materials is higher than that of an insulator, the MFM capacitor may have a higher capacitance than the MIS capacitor. Consequently, the MIS capacitance should be increased for efficient operation.
Possible ways to increase the MIS capacitance include the following approaches. First, the gate dielectric layer of the MIS capacitor, i.e., the insulator layer, may be thinned-down. Second, the gate dielectric of the MIS capacitor may be replaced with another material having high dielectric properties. And third, the physical area of the MIS capacitor may be made larger than that of the MFM capacitor.
In the past, the approach of increasing the physical area of the MIS capacitor led to the formation of an MFMIS FET device in the shape of an inverted-T (herein after referred to as “inverted T-shaped gate stack”), which required two photoresist masks in forming the word line. As shown in
FIG. 1
, an MFMIS FET device
100
in the prior art comprises a substrate
101
, a doped region
102
, a contact plug
103
, an isolation region
104
, and an inverted T-shaped gate stack
105
, including a first electrode layer
106
, a ferroelectric layer
107
, a second electrode layer
108
, an insulator layer
109
, and substrate
101
. MFMIS FeFET device
100
is formed using more than one word line mask—a first word line mask is used to etch second electrode layer
108
and insulator layer
109
, and a second word line mask is used to etch first electrode layer
106
and ferroelectric layer
107
, thus forming an MIS capacitor physically larger than an MFM capacitor. Increasing the number of word line masks increases the risk of leakage and short circuits as a result of misalignment and is incompatible with self-aligned contact etch processes commonly used for cell area reduction. To prevent leakage or a short circuit, isolation region
104
requires extra spacing between a contact plug
103
and an inverted T-shaped gate stack
105
to prevent, for example, shorts. Isolation region
104
may comprise, for example, a dielectric material.
To overcome the problems of the prior art, a MFMIS device with an inverted T-shaped gate stack formed using one word line mask and compatible with self-aligned contact processes is desired.
SUMMARY
In one embodiment of the invention, a method of forming a ferroelectric device comprises forming at least one active area on a silicon substrate by shallow trench isolation, depositing a plurality of layers on the at least one active area and a shallow trench isolation area, wherein the plurality of layers includes an insulator layer, a first electrode layer, a ferroelectric layer, a second electrode layer, and a first dielectric layer, etching at least one of the plurality of layers based on a word line mask to form a first etched layer and an unetched layer, forming a first spacer to define the first etched layer, etching at least a portion of the unetched layer based on the first spacer to form a second etched layer, forming a second spacer to define the second etched layer, forming an interlayer dielectric, opening a contact hole in the interlayer dielectric, and forming metal to fill the contact hole.
In another embodiment of the invention, a method of forming a ferroelectric device comprises forming at least one active area in a silicon substrate by shallow trench isolation, depositing a plurality of layers on the at least one active area and a shallow trench isolation are, wherein the plurality of layers includes an insulator layer, a first electrode layer, a ferroelectric layer, a second electrode layer, and a first dielectric layer, etching the first dielectric layer and second electrode layer based on a word line mask to form a first etched layer and an unetched layer, forming a first spacer to define the first etched layer, etching the ferroelectric layer based on the first spacer to form a second etched layer, forming a second spacer to define the second etched layer, etching at least the first electrode layer based on the second spacer to form a third etched layer, doping a first region of the active area and the shallow trench isolation area, wherein the first region is determined by the second spacer, forming a third spacer to define the third etched layer doping a second region of the active area and the shallow trench isolation area, wherein the second region is determined by the third spacer, depositing an interlayer dielectric, opening a contact hole in the interlayer dielectric, and depositing metal to fill the contact hole.
In yet another embodiment of the invention, a method of forming a ferroelectric device comprises forming at least one active area in a silicon substrate by shallow trench isolation, depositing a plurality of layers on the at least one active area and a shallow trench isolation area, wherein the plurality of layers includes an insulator layer, a first electrode layer, a ferroelectric layer, a second electrode layer, and a first dielectric layer, etching the first dielectric laye

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