Delay lock loop having an edge detector and fixed delay

Details Delay lock loop having an edge detector and fixed delay Delay lock loop having an edge detector and fixed delay

2002-03-19

2004-08-17

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06777990

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and, more particularly, to a delay lock loop circuit.
BACKGROUND OF THE INVENTION
Clock signals are used in virtually every integrated circuit (IC) to control the operational timing of the IC and/or the transfer of data within and between ICs. For example, all individual circuits or devices, such as, for example, flip-flops and/or latches, in a given IC may change state on a single rising or falling edge of a common clock signal. Relatively large ICs, such as, for example, memory chips, programmable logic arrays, or any other IC that requires clock skew adjustment, include thousands or even millions of such individual circuits or devices. The clock signal is typically applied to a clock input pin of the IC for distribution to each of those numerous devices throughout the IC. Thus, the clock signal is transmitted or propagated from the clock input pin to devices on the IC that are both relatively near to and relatively distant from the clock input pin. By the time the clock signal reaches the devices that are disposed on portions of the IC that are relatively remote from the input pin, the clock signal is likely to have suffered significant propagation delay.
The clock signal received at the IC clock input is hereinafter referred to as the input or reference clock signal REF_CLK, whereas the clock signal received by the last-served device on the IC is hereinafter referred to as the propagated clock signal P_CLK. The propagation delay between the REF_CLK and P_CLK signals, designated hereinafter as t
P
, may cause difficulties in interfacing between ICs and/or slow down the overall operating speed of a system. For example, data may be provided or input to an IC in a time-aligned manner with the reference clock signal, whereas data output from the IC is likely to be provided in a time-aligned manner with the propagated clock signal.
The propagation delay t
P
for a particular IC is dependent at least in part upon the configuration of that particular IC. Thus, for a given IC t
P
is generally fixed. However, t
P
will vary due to external factors, such as, for example, changes in ambient temperature, package temperature, and/or applied voltage. It is beneficial to compensate for the effect of such external factors on the propagation delay t
P
of the reference clock signal by aligning in time the propagated clock signal P_CLK of an IC with the reference clock signal REF_CLK. Delay lock loop circuits are one way in which such time alignment is performed.
Delay lock loop (DLL) circuits receive the reference clock signal REF_CLK and produce an output clock signal CLK_OUT that is advanced or delayed relative to the reference clock signal REF_CLK. For convenience, all signals produced by a DLL will hereinafter be referred to as being delayed relative to the REF_CLK signal regardless of whether the particular signal is actually advanced or delayed relative to the reference clock signal. A DLL delays the output clock signal CLK_OUT by an amount of time that is approximately equal to the propagation delay t
P
of the IC, i.e., the amount of time required for the reference clock signal REF_CLK to propagate through the IC under predefined operating conditions. Further, a DLL adjusts the CLK_OUT signal to compensate for changes in t
P
due to the aforementioned external factors. Devices formed on portions of the IC that are proximate the clock input pin are typically supplied with the REF_CLK signal, whereas devices formed on portions of the IC relatively distant from the input clock signal are typically supplied with the CLK_OUT signal. Thus, all devices on the IC receive time-aligned clock signals.
The DLL adjusts the amount of time by which the CLK_OUT signal is delayed relative to the REF_CLK signal by comparing the REF_CLK signal to a feedback clock signal FB_CLK. The FB_CLK signal is essentially a delayed version of the CLK_OUT signal. The FB_CLK signal is delayed by a feedback delay circuit that models the propagation delay through the integrated circuit. Thus, the time delay of the FB_CLK signal relative to the CLK_OUT signal is, for example, proportional or equal to the propagation delay t
P
of the IC. As the aforementioned external factors affect the propagation delay through the IC, the time delay introduced by the feedback delay circuit changes correspondingly.
The CLK_OUT signal is essentially a delayed version of the REF_CLK signal. The delay of the CLK_OUT signal is adjusted by a forward delay circuit having a forward delay line, such as, for example, a predetermined number of buffers or invertors connected together in series. The length of the forward delay line is adjusted based upon a comparison of the REF_CLK signal to the feedback clock signal FB_CLK, to thereby adjust the delay of the CLK_OUT signal and to align the CLK_OUT signal with the REF_CLK signal at the end of the clock tree. Thus, changes in the propagation delay due to the external factors are compensated for and the clock signals are aligned for a range of operating conditions and parameters.
In designing DLLs, a tradeoff between conflicting design goals has heretofore been required. The first design goal of a conventional DLL is to provide a maximum delay time approximately equal to the longest anticipated cycle time (i.e., the lowest operating frequency) of the REF_CLK signal to ensure alignment under worst-case operating conditions. The second design goal is to provide high resolution, i.e., small time increments, in the adjustment of the delay of the CLK_OUT signal, to maximize the alignment of the clocks and, therefore, the operating speed of the IC. Satisfying both of those goals requires a DLL having a delay line with a multitude of delay stages to thereby provide both high resolution and a wide frequency adjustment range.
However, as the resolution of the forward delay line increases the DLL must sequence through the delay line in correspondingly small time increments. Thus, compared to a DLL of lower resolution, a DLL having a high-resolution delay line requires a longer period of time to sequence through its correspondingly small time increments in order to reach a locked state. Further, such high-resolution delay lines consume relatively large amounts of valuable space on the substrate of the integrated circuit. Moreover, the entire length of the delay line is only utilized under worst case operating conditions.
Therefore, what is needed in the art is a DLL that achieves both the delay time required for worst-case operating conditions and a relatively high resolution, and yet has relatively few delay stages.
Furthermore, what is needed in the art is a DLL that achieves a locked state in a relatively short time period even under operating conditions approaching or equal to worst-case operating conditions.
SUMMARY OF THE INVENTION
The present invention provides a delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal that tracks changes in the propagation delay of an integrated circuit.
The invention comprises, in one form thereof, a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.
An advantage of the present invention is that a relatively high resolution is achieved with relatively few delay stages.
Another advantage of the present invention is that time alignment is achieved in a relatively short amount of time even under operating conditions equal to and approaching worst-case.


REFERENCES:
patent: 5463337 (1995-1

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