Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-03-21
2004-08-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
Reexamination Certificate
active
06777339
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for planarizing a deposited film by chemical mechanical polishing for use in production of a semiconductor device. More particularly, it relates to a method for forming a buried interconnect in a multi-layer interconnect process or forming an isolation region in an isolation process.
A method for forming a buried interconnect by the chemical mechanical polishing (CMP) will now be described as a conventional example with reference to
FIGS. 11A through 11C
and
12
A through
12
C.
First, as shown in
FIG. 11A
, an interconnect groove
3
is formed by photolithography and dry etching in an interlayer insulating film
2
of silicon dioxide deposited on a semiconductor substrate
1
. Thereafter, as shown in
FIG. 11B
, a barrier metal layer
4
of, for example, a tantalum nitride film is formed over the interlayer insulating film
2
including the inside faces of the interconnect groove
3
. The barrier metal layer
4
is thus formed in a small thickness over the interlayer insulating film
2
because copper used for forming a copper interconnect can easily diffuse into the silicon dioxide film of the interlayer insulating film
2
so as to degrade the insulating property of the interlayer insulating film
2
.
Next, as shown in
FIG. 1C
, a seed layer
5
of copper is formed on the barrier metal layer
4
by sputtering, and then, the seed layer
5
is grown into a copper film
6
by electroplating as shown in FIG.
12
A. In this case, the copper film
6
is grown to have a thickness larger than the depth of the interconnect groove
3
so that the interconnect groove
3
can be completely filled with the copper film
6
. Thus, an initial level difference
7
is formed in the copper film
6
above the interconnect groove
3
.
Then, as shown in
FIG. 12B
, an excessive portion of the copper film
6
present outside the interconnect groove
3
is removed by the CMP, thereby forming a buried interconnect
6
A from the copper film
6
. Finally, a portion of the barrier metal layer
4
present above the interlayer insulating film
2
is removed by the CMP as shown in FIG.
12
C.
Since tantalum nitride used for forming the barrier metal layer
4
for preventing diffusion of copper is a very stable material, it is difficult to simultaneously remove the copper film
6
and the barrier metal layer
4
by the CMP.
Accordingly, in order to form the buried copper interconnect
6
A, the copper film
6
and the barrier metal layer
4
should be separately polished. Specifically, at a first stage of the CMP, the copper film
6
alone is removed by the polishing and the polishing is stopped at the surface of the barrier metal layer
4
. A slurry used at the first stage of the CMP preferably has a polishing rate for tantalum nitride sufficiently higher than that for copper. Then, at a second stage of the CMP, the portion of the barrier metal layer
4
present above the interlayer insulating film
2
is removed by using a slurry suitable for polishing tantalum nitride. The slurry used at the second stage of the CMP preferably has a polishing rate for copper equivalent to or lower than that for tantalum nitride. Through the CMP thus carried out in the two stages, the buried interconnect
6
A can be formed without eliminating the copper film
6
.
FIG. 13A
shows an ideal cross-sectional shape of the buried copper interconnect
6
A, and
FIG. 13B
shows an actual cross-sectional shape of the buried copper interconnect
6
A. Specifically, the copper film
6
is polished during the CMP until the top face of the buried copper interconnect
6
A is placed at a level lower than that of the interlayer insulating film
2
. Accordingly, a plane face as shown in
FIG. 13A
cannot be obtained but unevenness designated as dishing is caused on the buried interconnect
6
A as shown in FIG.
13
B.
When the dishing is caused on the buried interconnect
6
A, a variety of problems may occur as follows: Since the height of the buried interconnect
6
A is lowered, the interconnect resistance may be increased. In forming a multi-layer interconnect structure, polishing residue of a copper film or a tantalum nitride film may be caused in a buried interconnect in an upper layer, which can cause short-circuit of the interconnect or can increase focal shift in the photolithography so as to cause a pattern defect.
Accordingly, in order to form a high performance buried interconnect, it is very significant to reduce dishing caused on the buried interconnect
6
A.
Alternatively, in forming an isolation region by filling an isolation groove with an insulating film in the isolation process, dishing may be caused on the isolation region. In this case, the isolation region is reduced in its thickness, and hence, a leakage defect may be caused between devices to be isolated or a pattern defect may be caused.
Accordingly, in order to form a high performance isolation region, it is very significant to reduce dishing caused on the isolation region.
There are some known causes for increase of dishing, against which countermeasures have been considered.
For example, the dishing tends to increase as the width of an interconnect is increased. This is because of elastic deformation of a polishing pad, and the upper limit in the width of an interconnect is provided at the stage of circuit design as the countermeasure.
Also, the dishing tends to increase as the polishing pad is softer. This is also because of the elastic deformation of the polishing pad, and a hard polishing pad is used as the countermeasure.
Furthermore, the dishing tends to increase as over-polishing is increased. The over-polishing is performed at the ultimate stage of the polarization process in order to completely remove an excessive portion of the copper film partly remaining on the substrate surface. The over-polishing is effective means for preventing short-circuit of an interconnect derived from polishing residue of the copper film and hence is indispensable, but excessive over-polishing may increase the dishing so as to increase the interconnect resistance and cause polishing residue in a buried interconnect in an upper layer. Therefore, the over-polishing should be sufficiently carefully performed. In other words, the over-polishing should be performed to a necessary and minimum extent. Excessive over-polishing is performed because of in-plane variation in the thickness of the deposited copper film and in-plane variation in the polishing rate in the CMP. Therefore, when such in-plane variations are reduced, the over-polishing can be avoided so as to reduce the dishing.
Another cause of increase of the dishing is the thickness of the copper film. Specifically, when the copper film has a too small thickness, an interconnect pattern is exposed before completely eliminating the initial level difference, and hence, the remaining initial level difference directly leads to the dishing of the interconnect. On the other hand, when the copper film has a too large thickness, the in-plane variation in the thickness of the copper film and the in-plane variation in the polishing rate in the CMP are both caused, and hence, the over-polishing is increased so as to increase the dishing.
SUMMARY OF THE INVENTION
In consideration of the aforementioned problems, an object of the invention is reducing dishing caused in completing over-polishing in the CMP.
In order to achieve the object, the method for planarizing a deposited film of this invention comprises the steps of forming a groove in a surface portion of a substrate; forming a deposited film on the substrate so as to fill the groove; eliminating an initial level difference formed in the deposited film due to the groove by subjecting the deposited film to a first stage of chemical mechanical polishing with a relatively high rotation speed and a relatively low pressure; and removing a portion of the deposited film present outside the groove after eliminating the initial level difference by subjecting the deposited film to a second stage of the chemical mechanical
Hoang Quoc
Matsushita Electric - Industrial Co., Ltd.
Nelms David
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