Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2003-03-25
2004-06-22
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S066000
Reexamination Certificate
active
06753549
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
Priority is claimed to Japanese patent application No. 2002-094665, filed Mar. 29, 2002, which is incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor and, more particularly, to a thin film transistor for use in a liquid crystal display device and others.
2. Prior Art
FIG.
7
(
a
) is a perspective view indicating a prior art thin film transistor while FIG.
7
(
b
) is a sectional view taken on line A-A′ of FIG.
7
(
a
).
In FIG.
7
(
a
), a reference numeral
1
indicates a thin film transistor,
2
a glass base plate,
3
an insulating foundation film made of silicon dioxide (SiO
2
) and others,
4
a semiconductor layer made of silicon (Si) for instance,
5
end portions located in the channel width direction of the semiconductor layer
4
,
6
a gate insulating film made of silicon dioxide and others,
7
a gate electrode,
8
a source region,
9
a drain region,
10
a channel region, L a channel length, W a channel width, and WD a width direction of the channel region. In FIG.
7
(
b
), a reference sign &thgr; designates a taper angle (i.e. a tilt angle &thgr; made by the hypotenuse and the horizontal side of the approximately right-angled triangular end portion) of the end portion
5
of the semiconductor layer
4
.
FIGS.
7
(
a
) and
7
(
b
) show the thin film transistor in which the semiconductor layer
4
is formed on the insulating foundation film
3
lying on the glass base plate
2
, and the gate electrode
7
is formed on the gate insulating film
6
as formed to cover the semiconductor layer
4
.
The thin film transistor having the gate electrode
7
above the semiconductor layer
4
as mentioned above is called a thin film transistor of the top-gate type.
In case of the top-gate type thin film transistor
1
as shown in FIGS.
7
(
a
) and
7
(
b
), if forming it for instance by using the semiconductor layer
4
made of silicon, due to the forming process of it, to put it concretely, the process of forming the semiconductor layer
4
in a predetermined pattern by etching it by means of the photolithographic method, both end portions
5
located in the channel width direction of the semiconductor layer
4
have a tapered shape, that is, a certain taper angle &thgr; as shown in FIG.
7
(
b
).
This taper angle &thgr; sometime varies depending on the location of the end portion on the glass base plate, due to the forming process as mentioned above. However, it is true that this variation in the taper angle &thgr; is a very important factor causing variation in the characteristic of the thin film transistor
1
.
As far as the channel width (or gate width) W is sufficiently wide, contribution of the end portion
5
(called gate edge portion) located in the channel region of the semiconductor layer
4
covered by the gate electrode
7
is relatively small, so that the variation of the taper angle &thgr; does not cause a significant problem.
However, if the channel width W becomes very small, for instance 1 &mgr;m or less, the issue that the characteristic of the thin film transistor
1
is dispersed due to the variation in the taper angle &thgr; appears before us as a problem to be considered and solve. Especially, in case of a glass base plate
2
having a large dimension for a liquid crystal display device use, this problem becomes more serious and significant.
Now, let us assume the thin film transistor
1
as shown in FIGS.
7
(
a
) and
7
(
b
) of which each part has a dimension as follows: the channel width W being 1 &mgr;m; a channel length L being 4 &mgr;m; the film thickness of the gate insulating film
6
being 40 nm; and the film thickness of the semiconductor layer being 60 nm.
A three-dimensional device simulation is executed with regard to the thin film transistor having the structure as mentioned above. FIGS.
6
(
a
) and
6
(
b
) are graphs showing results obtained by computing the data having been obtained from the three-dimensional device simulation. In the figures, FIG.
6
(
a
) shows a relation of Normalized Drain Current vs Gate Voltage (l
d
-l
g
characteristic) at taper angles of 30°, 45° and 60° while FIG.
6
(
b
) indicates the relation of Threshold Voltage vs Taper angle showing how the above taper angle &thgr; gives influence to the threshold voltage V
th
. In FIG.
6
(
a
), the drain voltage V
d
is 5V.
As will be clearly seen from these results, the l
d
-V
g
characteristic is remarkably changed by the taper angle &thgr; and the threshold voltage V
th
is also changed by the taper angle &thgr;. In short, this indicates that if the taper angle &thgr; is changed in the process of manufacturing the thin film transistor, the threshold voltage V
th
is changed. As will be apparent from FIG.
6
(
b
), the threshold voltage V
th
comes to indicate a considerably big change if the taper angle &thgr; is in the range of 60° or less while the change in the threshold voltage V
th
becomes very small if the taper angle &thgr; is in the range of more than 60°. From this, it will be understood how important the control of the taper angle &thgr; is.
Accordingly, an object of the invention is to provide a thin film transistor capable of controlling the dispersion in its characteristic, which is caused by the variation in the taper angle &thgr; at the end portion located in the channel width direction of the semiconductor layer.
SUMMARY OF THE INVENTION
In order to solve the problems as described above, the invention takes constitutions as recited in the scope of claim for patent attached to this specification.
That is, a thin film transistor as recited in claim
1
includes a semiconductor layer formed on a base substrate, a source region and a drain region formed on the semiconductor layer to be separately located on both sides in the longitudinal direction of the semiconductor layer, a channel region located between the source region and the drain region, and a gate electrode formed on a gate insulating film lying on the channel region, wherein the taper angle &thgr; of each of end portions located in the channel width direction in the channel region covered by at least the gate electrode is 60° or more.
Furthermore, a thin film transistor as recited in claim
2
includes a semiconductor layer formed on a base plate, a source region and a drain region formed on the semiconductor layer to be separately located on both sides in the longitudinal direction of the semiconductor layer, a channel region located between the source region and the drain region, and a gate electrode formed on a gate insulating film lying on the channel region, wherein each of end portions located in the channel width direction in the channel region covered by at least the gate electrode is insulated.
Still further, a thin film transistor as recited in claim
3
includes a semiconductor layer formed on a base plate, a source region and a drain region formed on the semiconductor layer to be separately located on both sides in the longitudinal direction of semiconductor layer, a channel region located between the source region and the drain region, and a gate electrode formed on a gate insulating film lying on the channel region, wherein an impurity having a conductive type opposite to that which is introduced into the source region and the drain region as well, is introduced into the end portion located in the channel width direction in the channel region at least covered by at least the gate electrode.
A thin film transistor according to the invention will now be described in detail by way of several embodiments thereof with reference to the accompanying drawings in which constituents of the invention having like function are designated by like reference numerals and signs, and repetitive description thereof will be omitted for simplification.
REFERENCES:
patent: 4546376 (1985-10-01), Nakata et al.
patent: 5739574 (1998-04-01), Nakamura
patent: 6184556 (2001-02-01), Yamazaki et al.
patent: 2001/0036710 (2001-11-01), Hayashi et al.
Graybeal Jackson Haley LLP
Kabushiki Kaisha Ekisho Sentan Gijutsu Kaihatsu Center
Ngo Ngan V.
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