Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-08-29
2004-12-14
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S709000, C438S723000, C438S725000, C438S743000
Reexamination Certificate
active
06831019
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes, and to plasma etching methods.
BACKGROUND OF THE INVENTION
Semiconductor fabrication continues to strive to make individual electronic components smaller and smaller, resulting in ever denser integrated circuitry. One type of integrated circuitry comprises memory circuitry where information is stored in the form of binary data. The circuitry can be fabricated such that the data is volatile or non-volatile. Volatile memory circuitry loses stored data when power is interrupted, while non-volatile memory circuitry retains stored data even when power is interrupted.
U.S. Pat. Nos. 5,761,115; 5,896,312; 5,914,893; and 6,084,796 to Kozicki et al. disclose what is referred to as a programmable metallization cell. Such a cell includes opposing electrodes having an insulating dielectric material received therebetween. Received within the dielectric material is a variable resistance material. The resistance of such material can be changed between low resistance and high resistance states. In its normal high resistance state, to perform a write operation, a voltage potential is applied to a certain one of the electrodes, with the other of the electrodes being held at zero voltage or ground. The electrode having the voltage applied thereto functions as an anode, while the electrode held at zero or ground functions as a cathode. The nature of the resistance variable material is such that it undergoes a change at a certain applied voltage. When such a voltage is applied, a low resistance state is induced into the material such that electrical conduction can occur between the top and bottom electrodes.
Once this has occurred, the low resistance state is retained even when the voltage potential has been removed. Such material can be returned to its highly resistive state by reversing the voltage potential between the anode and cathode. Again, the highly resistive state is maintained once the reverse voltage potentials are removed. Accordingly, such a device can, for example, function as a programmable memory cell of memory circuitry.
The preferred resistance variable material received between the electrodes typically and preferably comprises a chalcogenide material having metal ions diffused therein. One specific example includes one or more layers of germanium selenide (Ge
x
Se
y
) having silver ions diffused therein.
Currently, etching of germanium selenide (Ge
x
Se
y
) is conducted using a halogen containing etching gas, for example chlorine, fluorine, or compounds which include elemental chlorine and/or fluorine. However, such etching methods have limitations, and there remains a need for new plasma etching methods, and for additional methods of forming memory devices comprising a chalcogenide comprising layer.
While the invention was principally motivated in addressing the above issues, it is in no way so limited. The artisan will appreciate applicability of the invention in other aspects unrelated to the above issues, with the invention only being limited by the accompanying claims as literally worded without limiting reference to the specification, and as appropriately interpreted in accordance with the doctrine of equivalents.
SUMMARY
Methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate a pair of conductive electrodes are described. Plasma etching methods are also described. In one implementation, a Ge
x
Se
y
chalcogenide comprising layer is formed over a substrate. A pair of conductive electrodes is provided operably proximate the Ge
x
Se
y
chalcogenide comprising layer. Plasma etching of the Ge
x
Se
y
chalcogenide comprising layer is conducted utilizing an etching gas comprising at least one of NH
3
, N
2
H
4
and C
x
H
y
.
In one implementation, a method includes forming a Ge
x
Se
y
chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the Ge
x
Se
y
chalcogenide comprising layer. The mask comprises a first sidewall. The Ge
x
Se
y
chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. Such forms a layer on the first sidewall and forms a second sidewall laterally outward of the first sidewall. The plasma etching forms a substantially vertical sidewall of the Ge
x
Se
y
chalcogenide comprising layer which is aligned with a lateral outermost extent of the second sidewall.
In one implementation, a plasma etching method comprises forming a Ge
x
Se
y
chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the Ge
x
Se
y
chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the Ge
x
Se
y
comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After said exposing, the Ge
x
Se
y
chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the Ge
x
Se
y
chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.
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Gilton Terry L.
Ko Kei-Yu
Li Li
Moore John T.
Signorini Karen
Dickstein , Shapiro, Morin & Oshinsky, LLP
Duong Khanh
Micro)n Technology, Inc.
Zarabian Amir
LandOfFree
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