Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-02-10
2004-06-22
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S620000, C257S127000, C438S624000
Reexamination Certificate
active
06753608
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a passivation film and a seal for an edge of a die which serve as a protective structure for a semiconductor device.
2. Description of the Background Art
In order to protect a region in which a circuit is formed (hereinafter, referred to as a “circuit region”) in a semiconductor device from influences of moisture and ions contained in an ambient air, a protective structure called a “die edge seal”, “guard ring” or “seal ring” is provided on an inner side of a dicing line, that is, in the vicinity of an edge portion of a chip (die). A typical seal ring is formed of interconnect layers and contacts made of materials in the same manner as a circuit region in a semiconductor device, and surrounds the circuit region. Further, a protective film called a “passivation film” is provided on a surface of the semiconductor device to function to protect the surface of the semiconductor device, keeping the surface of the semiconductor device away from influences of an ambient air.
In recent days, a semiconductor device has been structurally further miniaturized, and an integration density as well as an operation speed thereof has been further increased. Under such a condition, higher importance has been placed on reduction of interconnect resistance. As a result, copper (Cu) having a relatively low resistance has been more frequently utilized as a material for interconnects. Accordingly, copper has been utilized also to form the above-mentioned seal ring in more instances.
FIG. 29
is a view illustrating a structure of a conventional semiconductor device, more particularly, is an enlarged view of an area of the conventional semiconductor device in which a seal ring is formed. As described above, a seal ring is typically formed on an inner side of a dicing line. The area illustrated in
FIG. 29
includes a circuit region on the left-hand side of the drawing and includes a dicing region (a region to be cut during dicing) on the right-hand side of the drawing. It is noted that circuit elements of the semiconductor device are omitted in FIG.
29
.
Referring to
FIG. 29
, a seal ring
110
includes a first contact
111
, a first interconnect layer
112
, a second contact
113
and a second interconnect layer
114
. On a silicon substrate
101
having an isolation film
102
formed therein, an interlayer insulating film
103
having the first contact
111
formed therein, an interlayer insulating film
105
having the first interconnect layer
112
made of copper formed therein, an interlayer insulating film
107
having the second contact
113
formed therein and an interlayer insulating film
109
having the second interconnect layer
114
made of copper formed therein are formed. Further, etch stop layers
104
,
106
and
108
are formed between the interlayer insulating films
103
and
105
, the interlayer insulating films
105
and
107
, and the interlayer insulating films
107
and
109
, respectively.
Each of the first and second contacts
111
and
113
is made of tungsten (W), for example, while each of the interlayer insulating films
103
,
105
,
107
and
109
is made of plasma oxide, for example. Each of the etch stop layers
104
,
106
and
108
is made of plasma nitride, for example.
Moreover, a passivation film
120
is formed on the uppermost interlayer insulating film. In an instance illustrated in
FIG. 29
, the passivation film
120
has a bilayer structure composed of a layer of plasma nitride (plasma nitride layer)
121
and a polyimide layer
122
.
Because of provision of the seal ring
110
and the passivation film
120
, the circuit region of the semiconductor device is protected from influences of moisture and ions contained in an ambient air, which makes it possible to ensure stability of properties of the semiconductor device over a long period of time.
Also, the seal ring
110
produces a further effect of preventing a crack from occurring in the circuit region at a time of cutting the dicing region during dicing. A crack which possibly occurs in the dicing region during dicing is prevented from propagating from the dicing region to the circuit region, because of provision of the seal ring
110
between the dicing region and the circuit region.
In the conventional semiconductor device, the passivation film
120
is formed only on one side of the seal ring
110
where the circuit region is provided (a circuit region side). Accordingly, on the other side where the dicing region is provided (a dicing region side), a top face of the interlayer insulating film
109
is exposed. Such configuration is employed in the conventional semiconductor device for the following reasons. If the passivation film
120
is formed on an entire surface of a wafer including the dicing region, a stress (or a crack) occurring in the dicing region due to a process of cutting the dicing region during dicing can easily propagate through the passivation film
120
to the circuit region, so that a crack is more likely to occur in the circuit region.
For the foregoing reasons, the conventional semiconductor device employs a configuration in which a top face of the uppermost layer of the seal ring
110
, i.e., the second interconnect layer
114
, is exposed as illustrated in FIG.
29
. Accordingly, the top face of the second interconnect layer
114
is exposed to an ambient air in the conventional semiconductor device. When the uppermost layer of the seal ring
110
, i.e., the second interconnect layer
114
, is made of copper as in the instance of
FIG. 29
, the foregoing conventional configuration disadvantageously results in oxidation and corrosion of the second interconnect layer
114
because copper is more easily to be oxidized and corroded than other kinds of metal as a material for interconnects (such as aluminum). This invites reduction of the effect of protecting the semiconductor device which is achieved by the seal ring
110
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of preventing a crack from occurring in a circuit region during dicing, while preventing a seal ring from being oxidized and corroded.
According to a first aspect of the present invention, a semiconductor device includes a seal ring and a passivation film. The seal ring is formed in an interlayer insulating film in the vicinity of an edge portion of a semiconductor chip, and surrounds a circuit region of the semiconductor chip. The passivation film is formed above the seal ring so as to cover a surface of the semiconductor chip, and has a first opening reaching a top face of the interlayer insulating film. Further, a top face of an uppermost layer of the seal ring is covered with the passivation film.
The top face of the uppermost layer of the seal ring portion is not exposed to an ambient air. Accordingly, even if copper, for example, is employed as a material for the uppermost layer of the seal ring, it is possible to prevent an effect of protecting the semiconductor device achieved by the seal ring from being reduced due to oxidation and corrosion of the uppermost layer. Further, because of provision of a region not including the passivation film, a stress generated at a time of cutting a dicing region during dicing can not easily propagate to a portion of the passivation film which is present on a circuit region. Hence, it is possible to prevent a crack from occurring in the circuit region.
According to a second aspect of the present invention, a semiconductor device includes a seal ring, an aluminum interconnect layer and a passivation film. The seal ring is formed in an interlayer insulating film in the vicinity of an edge portion of a semiconductor chip, and surrounds a circuit region of the semiconductor chip. The aluminum interconnect layer is formed on the seal ring. The passivation film is formed above the seal ring so as to cover a surface of the semiconductor chip, and has a first opening reaching a top face of the interlayer insulating film. Further, a to
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