Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With means to increase breakdown voltage
Reexamination Certificate
1999-04-23
2004-02-24
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With means to increase breakdown voltage
C257S328000, C257S339000
Reexamination Certificate
active
06696707
ABSTRACT:
TECHNICAL FIELD
The present invention relates to high voltage integrated switching devices and to methods of fabricating several of such devices on a single silicon substrate.
BACKGROUND OF THE INVENTION
The term “breakdown voltage”, as used herein, means the voltage required to cause current to leak through a dielectric insulator, thereby causing a short circuit between inadequately dielectrically isolated devices or components. The term “high voltage”, as used herein, means a device which has a breakdown voltage of at least 100 volts, and possibly much greater. The term “intermediate voltage”, as used herein means a device which has a breakdown voltage from approximately 20 volts up to approximately 100 volts. The term “low voltage”, as used herein means a device which has a breakdown voltage less than and up to approximately 20 volts.
High-voltage switching applications in, for example, telephone central office switching stations generally require a large number of high-voltage switching circuits on a single circuit board. The density and proximity of several high-voltage circuits on a single board requires adequate dielectric isolation between them to avoid shorting of the individual circuits.
High voltage circuits are preferably dielectrically isolated in both the vertical and lateral directions. Vertical isolation techniques are well known in the semiconductor manufacturing industry, and adequate vertical isolation is not difficult to achieve. However, adequate lateral isolation in a relatively confined space has been much more difficult to achieve.
In the past, such dielectric isolation has generally been provided by locating the individual switching circuits a substantial lateral distance apart from one another and by filling the inter-circuit spaces with a dielectric insulating material.
The higher the voltage rating of a device, the greater the dielectric isolation required between adjacent devices. To prevent premature breakdown of adjacent devices due to the magnitude of the electric fields from each of the devices, a dielectric filler material is preferably used to fill the spaces between the devices. The breakdown voltage of a device is a function of the amount of dielectric material between adjacent high voltage devices. Using this isolation approach, optimal spacing of high voltage devices therefore may require relatively great amounts of dielectric isolation material between and around them, and this in turn requires that the devices be more widely spaced apart over a larger area.
The use of bonded and vertically trenched silicon substrates in the fabrication of multiple high voltage devices allows adjacent devices to be spaced as closely as 3 micrometers from one another in the lateral direction. Vertical trenching processes are well known and disclosed in, for example, U.S. Pat. No. 4,139,442 to Bondur et al. With anisotropic etching, the extent of material removal in the lateral direction can be more closely controlled and is generally less than the extent of material removal in the vertical direction. This is highly advantageous in controlling manufacturing costs and increasing throughput in the fabrication of low voltage devices. However, such substrates have heretofore not been used in the fabrication of multiple high voltage devices.
It would therefore be advantageous to provide a high voltage integrated switching device which includes, for example, multiple high-voltage circuits or a variety of high-, medium- and low-voltage circuits, on a single bonded and vertically trenched silicon substrate.
SUMMARY OF THE INVENTION
According to one aspect of the invention, there is provided a high voltage integrated switching device, comprising a dielectrically isolated, bonded and vertically trenched silicon substrate, and at least one high voltage switching circuit fabricated on the substrate. The high voltage switching circuit is characterized by a breakdown voltage of at least 100 volts or greater.
In a preferred embodiment, the high voltage switching circuit is a bidirectional switching circuit that is characterized by a breakdown voltage of at least 350 volts.
The high voltage switching circuit preferably employs double diffused metal oxide semiconductor (DMOS) technology.
The device can include one or more intermediate and/or low voltage circuits on the same substrate. In one embodiment the intermediate voltage circuit preferably employs bipolar technology, and the low voltage circuit preferably employs complementary metal oxide semiconductor (CMOS) technology.
According to another aspect of the invention, there is provided a method of making a high voltage integrated switching device. The method comprises the steps of:
providing a bonded pair of silicon wafers separated by a layer of insulating silicon dioxide;
forming a network of substantially vertical trenches in one wafer of the bonded pair to define a plurality of silicon active regions, and dielectrically isolating the silicon active regions from one another;
doping the silicon active regions with a dopant material of the same conductivity type to form tubs, each including a silicon wraparound layer having a relatively high concentration of that conductivity type on the floors and sidewalls of the tubs; and
fabricating at least one high voltage switching circuit in at least one of the silicon active regions.
In one preferred embodiment, the step of fabricating the at least one high voltage switching circuit comprises the following steps:
forming a layer of highly pure silicon dioxide over a silicon active region;
forming a layer of polycrystalline silicon over the silicon dioxide layer; exposing selected portions of the silicon dioxide and polycrystalline silicon layers;
forming at least one p-type region within the exposed portions by implanting a p-type dopant therein;
forming at least one n-type region within each of the p-type regions to define source contacts for the high voltage circuit, and forming an n-type region bridging the silicon active region and the wraparound region, by implanting an n-type dopant therein, to define a drain contact for the high voltage circuit; and
forming electrically conductive contact pads over each of the source and drain contacts of the high voltage circuit.
In one preferred embodiment, the p-type dopant includes an element selected from the group consisting of arsenic and phosphorus. The p-type dopant preferably, although not necessarily, includes boron.
The method can further include the steps of fabricating at least one of an intermediate voltage and/or a low voltage circuit in respective silicon active regions during fabrication of the high voltage switching circuit, and on the same substrate.
In one preferred embodiment, the step of fabricating the intermediate voltage circuit comprises the steps of:
forming at least one p-type region within the silicon active region by implanting a p-type dopant therein;
forming an n-type region within the p-type region to define an emitter, and forming an n-type region within the silicon active region outside of the p-type region to define a collector, the n-type region extending from the silicon active region to the n+ wraparound region;
forming a p+ region within the p-type region to define a base; and
forming electrically conductive contact pads over the collector, emitter and base of the bipolar circuit.
In one preferred embodiment, the step of fabricating the low voltage circuit preferably comprises the steps of:
defining an n-channel and a p-channel in respective adjacent silicon active regions;
forming at least one p-type region within the silicon active region of the n-channel by implanting a p-type dopant therein;
forming a layer of highly pure silicon dioxide on the surfaces of the p-type region and the silicon active regions of the n-channel and p-channel;
forming a layer of polycrystalline silicon over the silicon dioxide layer; forming at least one source contact and at least one drain contact in the p-channel by implanting a p-type dopant into selected portions of the p-channel;
forming at least on
Heisig Mark F.
Jones Scotten W.
Polce Nestore A.
CCP. Clare Corporation
McDermott & Will & Emery
Owens Douglas W.
Thomas Tom
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