Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-26
2004-11-23
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S207000, C327S052000, C327S053000
Reexamination Certificate
active
06822906
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention broadly relates to an electronic multi-level non-volatile memory device, which is monolithically integrated in a semiconductor and includes a circuit structure for reading data from the memory.
The invention relates to a sense amplifier structure for reading non-volatile memories, in particular multi-level flash EEPROMs.
Specifically, the invention relates to a sense amplifier for multi-level non-volatile memories arranged as cell arrays or matrix, said sense amplifier including at least one differential stage having an input terminal connected to a circuit node receiving a current drawn by a memory cell to be read and a current drawn by a reference cell for comparison.
The invention further relates to a method of accurately reading data from multi-level non-volatile memories, wherein a current drawn by a memory cell to be read and a current drawn by a reference cell are compared to each other by means of a sense amplifier having an input terminal connected to a circuit node to which both currents are led.
2. Description of the Related Art
As is known in this technical field, the most recent developments in the field of non-volatile memories, in particular of the EPROM, EEPROM and flash types, trend toward providing increased storage capacity through the use of multi-level architectures, i.e., memory matrix whose cells can store plural logic states.
However, the aspects of this invention can be more clearly understood if the circuit constructions of classic two-level memories are first reviewed briefly.
Electronic memory devices usually comprise at least one array of memory cells arranged into rows and columns in the array; logic information can be written into, or read from, each cell by suitably biasing its corresponding row and column.
A typical memory cell comprises a field-effect transistor having a control gate terminal, a floating gate region coupled capacitively to the control gate, a source terminal, and a drain terminal. The two attainable logic states of a two-level memory cell, e.g., a logic “0” to denote a programmed cell and a logic “1” to denote an erased cell, are separated by a range of potential.
The informational contents of a two-level non-volatile memory cell is discriminated by comparison with a reference cell, the latter being an identical structure with the former, except that its state is intermediate with respect to the two allowed logic states for the matrix cells.
The operation of selecting a memory cell to read its informational contents consists of applying a suitable bias voltage to the control gate terminal of the cell. If the cell has been programmed, an electric charge is caught in the floating gate region, and the threshold voltage of the cell is such that the cell will conduct a lower drain current than the reference cell.
By converse, if the cell has been erased, no electric charge is caught in the floating gate region, and the cell will conduct a larger drain-source current than the reference cell.
Thus, the most widely used method of reading a flash memory cell comprises comparing the current drawn by the cell to be read with the current drawn by the reference cell. A simple comparator, known as the sense amplifier, makes the comparison and correspondingly outputs a result. The sense amplifier is to compare the cell current draw with the current drawn by the reference cell, thereby converting the analog information of the addressed data to a digital form.
In multi-level memories, n bits per cell are stored, it being n>1. This greatly enhances the array efficiency as concerns its storage capacity per unit area. Accordingly, in the instance of a multi-level memory device, at least 2
n
−1 references are needed in order to discriminate a cell having a storage capacity of n bits, which references may be either voltage or current references according to the reading method being used.
Exemplary of the state of the art is a technique for determining the state of an n-level memory cell disclosed in U.S. Pat. No. 5,774,395, which is incorporated by reference in its entirety.
A key factor in the design of multi-level memories is its read circuitry, and there are essentially two modes that can be used: the serial or the parallel mode.
To store n bits into a multi-level cell, the cell must have 2{circumflex over ( )}n attainable states: for instance, 4 states must be allowed when 2 bits are to be stored.
Two cells having different states differ from each other by the charge that is stored in their floating gate, and hence by their threshold. Typically, to determine the state of a multi-level cell, the cell has to be compared with 2{circumflex over ( )}n−1 reference cells. The comparison may be performed in the serial or the parallel mode, as mentioned above.
The parallel mode is preferred whenever read time is required to be very short. For instance, when two bits per cell are to be stored, three sense amplifiers must be provided for each bit pair of the byte being read. The three sense amplifiers will compare the currents of three reference cells R
1
, R
2
, R
3
with the current of the selected cell in the array.
FIG. 1
a
shows a basic circuit diagram for a sense amplifier circuit structure
1
that is intended for a single-level memory. It can be seen that the comparison between the current drawn by an array cell and that drawn by a reference cell is performed at an input terminal I
1
of a differential stage
2
. The other input terminal I
2
is biased to a constant voltage. The current difference generates a differential voltage at the input of the differential stage
2
. The output of the differential stage
2
is connected to an inverter
3
, and is initially precharged to a voltage level that will set the inverter
3
for maximum gain.
FIG. 1
b
shows in greater detail the construction of the differential stage of
FIG. 1
a
, and
FIG. 1
c
shows schematically the types of signal that appear in the differential stage and the inverter placed after it.
During the precharging step, a signal deprech will be at a high logic level and its negation, deprech-n, at a low logic level. When the signals deprech and deprech-n are switched, the output from the differential stage
2
, represented by a node outdiff, is left to itself and allowed to float. This output will vary its voltage with the output current of the differential stage
2
, and the variation will be amplified by the inverter
3
. The output from the inverter
3
is stored into a latching register
4
that is controlled by signals salatch and salatch-n. For the reading to be successful, the variation at the input of the inverter
3
must be larger than its transition range.
One comparison term between different sense amplifier designs, and one that is vital to multi-level memories, is precision. The precision of a sense amplifier grows inversely with the current gap between the cell to be read and the reference cell; a minimum gap will ensure successful reading.
This precision should be correlated with the sense amplifier timing, because precision increases with acquisition time.
Thus, a comparison of different sense amplifier architectures should be performed under the same conditions of memory data acquisition time.
While being advantageous on several counts, the above prior art still leaves something to be desired from the standpoint of data acquisition accuracy.
BRIEF SUMMARY OF THE INVENTION
An embodiment of this invention provides both a method of reading data from a multi-level non-volatile memory and an associated sense amplifier structure with appropriate design and functional features to ensure accurate reading and overcome the limitations that beset the performance of prior sense amplifiers.
The method performs a comparison of currents at both input terminals of the differential stage of the sense amplifier.
The features and advantages of the sense amplifier structure and data reading method of this invention will be more clearly apparent from the following description of embodiments there
Iannucci Robert
Jorgenson Lisa K.
Nguyen Tan T.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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