Dynamic magnetic information storage or retrieval – General processing of a digital signal – Data clocking
Reexamination Certificate
2001-05-25
2004-02-10
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Data clocking
C331S025000, C375S376000, C377S052000, C713S502000
Reexamination Certificate
active
06690525
ABSTRACT:
BACKGROUND
Computer hard disk drives, also known as fixed disk drives or hard drives, have become a de facto data storage standard for computer systems. Their proliferation can be directly attributed to their low cost, high storage capacity and reliability, in addition to wide availability, low power consumption, fast data transfer speeds and decreasing physical size.
Disk drives typically include one or more rotating magnetic platters encased within an environmentally controlled housing. The hard drive may have several read/write heads that interface with the magnetic platters. The disk drive may further include electronics for reading and writing data and for interfacing with other devices. The electronics are coupled with the read/write heads and include circuits to control head-positioning and to generate or sense electromagnetic fields on the platters. The electronics encode data received from a host device, such as a personal computer, and translate the data into magnetic encodings, which are written onto the platters. When data is requested, the electronics locate the data, sense the magnetic encodings, and translate the encodings into binary digital information. Error checking and correction may also be applied to ensure accurate storage and retrieval of data.
The read/write heads detect and record the encoded data as areas of magnetic flux. The data are encoded by the presence or absence of a flux reversal between two contiguous areas of the platter. Data may be read using a method known as “Peak Detection” by which a voltage peak imparted in the read/write head is detected when a flux reversal passes the read/write head. However, increasing storage densities, requiring reduced peak amplitudes, better signal discrimination and higher platter rotational speeds are pushing the peaks in closer proximity. Thus, peak detection methods are becoming increasingly complex.
Advancements in read/write heads and in the methods of interpreting magnetic encodings have been made. For example, magneto-resistive (“MR”) read/write heads have been developed. MR heads have been designed with increased sensitivity and increased signal discrimination. In addition, technology known as Partial Response Maximum Likelihood (“PRML”) has been developed. PRML based disk drives function based an algorithm implemented in the disk drive electronics to read analog waveforms generated by the magnetic flux reversals. Instead of looking for peak values, PRML based drives digitally sample the analog waveform (the “Partial Response”) and carry out advanced signal processing techniques to determine a most-likely bit pattern represented by the wave form (the “Maximum Likelihood”). PRML technology tolerates more noise in the magnetic signals, permitting use of lower quality platters and read/write heads, which also increases manufacturing yields and lowers costs.
With hard drives typically differentiated by factors such as cost/unit of storage, data transfer rate, power requirement, and form factor (physical dimensions), there is a need for enhanced hard drive components which prove cost effective in increasing storage capacity, operating speed, reliability and power efficiency. For example, PRML electronics may include a phase locked loop (“PLL”) that provides a feedback clock signal used to synchronize read and write operations for the PRML based hard drive. The feedback clock signal may be derived by a counter from a output clock signal of a Voltage Controlled Oscillator (“VCO”). The counter, also referred to as a divider, derives the feedback clock signal by generating a clock pulse when a desired number of the high-speed clock pulses have been counted. Accordingly, the counter provides a feedback clock signal having a modulus frequency of the output clock.
With the VCO output clock signal frequency increasing, a need for larger counters to provide a feedback clock signal having a desired modulus frequency of the VCO output clock signal frequency also increases. However, as the counter size grows, the counter speed of the counter decreases. Counter designs may provide increased speed but are not programmable.
Accordingly, there is a need in the art for a high-speed programmable synchronous counter.
SUMMARY
A high-speed programmable synchronous counter which may be used in a partial response, maximum likelihood (“PRML”) read/write channel is disclosed. The counter, also referred to as a divider, may be provided in a feedback circuit of a Phase Locked Loop (“PLL”). The counter derives a feedback clock signal from an output clock signal of a Voltage Controlled Oscillator (“VCO”) of the Phase Locked Loop (“PLL”).
An embodiment for a programmable synchronous high-speed counter includes a clock input; a least-significant-bit counter; a most-significant-bit counter; a count input circuit; and a counter output circuit. The clock input may be configured to receive a clock signal at an input node. The clock signal may be a high-speed output clock provided by a VCO.
The least-significant-bit counter may be coupled with the clock input node. The least-significant-bit counter is configured to decrement a least-significant-bit count value in response to a clock signal. The least significant-bit counter further provides a signal at an output node for the least significant-bit counter when the least significant-bit counter decrements to a zero-count value.
The most-significant-bit counter may be coupled with the least-significant-bit output node. When the least-significant-bit counter provides the zero-count signal at the output node, the most-significant-bit counter decrements a most-significant-bit count value. The most-significant-bit counter also provides a signal at an output node for the most-significant-bit zero when the most-significant-bit counter decrements to a zero-count value.
The least-significant-bit counter may be further coupled with the output node for the most-significant-bit counter. The least-significant-bit counter resets to a highest count value for the least-significant-bit counter, when the least-significant-bit counter has a zero-count value and the most-significant-bit output signal has a non-zero count value. The least-significant-bit and most significant bit counters reload to an initial state when the least-significant-bit and most-significant-bit counters have a zero count value.
The count input circuit receives a count value that is to be programmed into the counter. The count value is includes least-significant bits and most-significant bits. The count input circuit programs the initial state for the least-significant-bit counter with the least significant bits and the initial state for the most-significant-bit counter with the most significant bits.
The counter output is coupled with the outputs of the least-significant-bit counter and the most-significant-bit counter. The counter output circuit provides a clock pulse at a counter output node in response to the least-significant-bit zero state signal and the most-significant-bit zero state signal.
An embodiment of a method for counting high-speed clock pulses includes the acts of: receiving a clock signal; receiving a count value including least significant bits and most significant bits; programming a least-significant-bit counter with the least-significant bits and a most-significant-bit counter with the most-significant bits; decrementing the least-significant-bit counter in response to the clock signal and generating a least-significant-bit zero-count signal when the least-significant-bit counter has a zero value; decrementing the most-significant-bit counter in response to the least-significant-bit zero-count signal and generating a most-significant-bit zero-count signal when the most-significant-bit counter has a zero value; and generating an output signal in response to the least-significant-bit zero-count signal and the most-significant-bit zero-count signal.
The foregoing discussion of the summary of the invention is provided only by way of introduction. Nothing in this section should be taken as a limitation on the claims, wh
Cyrusian Sasan
Ruegg Michael A.
Faber Alan T.
Infineon - Technologies AG
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