Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-01-31
2004-10-19
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S763000
Reexamination Certificate
active
06806574
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of reducing electromigration occurring in multilevel interconnections of a high-speed integrated circuit that has a small-sized feature according to submicron design rules, and a method of manufacturing the same.
2. Description of the Related Art
As semiconductor devices are becoming more highly integrated, there is an increase in a need for multilevel interconnections. In the event that a multilevel interconnection structure is adopted in a highly integrated semiconductor memory device, thick interlayer insulating films are interposed between interconnections in order to minimize parasitic capacitance between the interconnections. As a result, in the multilevel interconnections having such thick interlayer insulating films, contacts or vias are formed to have a large aspect ratio for electrically connecting interconnection layers that are formed to have feature sizes according to submicron design rules and that are placed above and below the interlayer insulating films.
There are means by which the resistivity of a conductive pattern can be reduced in order to increase a control speed in a highly integrated semiconductor device having multilevel interconnections. In the past, a semiconductor device was manufactured mainly using aluminum for forming multilevel interconnection vias because aluminum is comparatively inexpensive, has a low resistivity, and can be easily etched. However, in this case, as the size of holes for forming vias became scaled-down to a submicron level, step coverage became inadequate using aluminum. To solve these problems, a metal interconnection layer can be formed of aluminum, and a via, which electrically connects metal interconnection layers placed in different levels, can be formed of tungsten w which is deposited by a chemical vapor deposition (CVD) method. However, in this case, some problems may occur. That is, electromigration occurs in an aluminum interconnection layer which is adjacent to the vias made of tungsten. Electromigration is a phenomenon whereby conductive ions such as aluminum ions move in the direction of electric current flow. Due to electromigration, a void is formed on an aluminum interconnection layer which is adjacent to the via and has a low electric potential. As the size of the void is increased, the interconnections are eventually disconnected. Further, when the void is formed on one end of the via, an electric current flowing through the aluminum interconnection layer is increased or the operational temperature of the semiconductor device is raised. In view of this, there is a higher probability that interconnections are disconnected, and thus, the semiconductor device malfunctions. Also, a contraction in the width of an interconnection results in an increase in the amount of electric current flowing through the interconnection, and electromigration is thus worsened, thereby increasing the likelihood of disconnecting the interconnections.
SUMMARY OF THE INVENTION
To address the above limitations, a first objective of the present invention is to provide a semiconductor device having multilevel interconnections, which is capable of reducing electromigration.
A second objective of the present invention is to provide a method of manufacturing a semiconductor device having multilevel interconnections and capable of reducing electromigration.
Accordingly, to achieve the first objective, there is provided a semiconductor device including multilevel interconnections. In the semiconductor device, a first metal interconnection layer is formed on a semiconductor substrate. A second metal interconnection layer is formed on the first metal interconnection layer. An intermetal insulating film is interposed between the first and second metal interconnection layers. The first and second metal interconnection layers are electrically connected with each other by a contact stud. The contact stud is composed of a first portion penetrating the intermetal insulating film and a second portion protruding above the intermetal insulating film. The second portion has vertical sidewalls that are extended vertically with respect to the main surface of the semiconductor substrate and an upper surface that is extended parallel to the main surface, and the vertical sidewalls and upper surface are entirely covered with the second metal interconnection layer.
The first metal interconnection layer may be formed of one of aluminum and an aluminum alloy and the second metal interconnection layer may be formed of one of aluminum and an aluminum alloy. The contact stud may be formed of tungsten w.
The semiconductor device according to the present invention may further include an adhesive layer interposed between the second portion of the constant stud and the second metal interconnection layer. The adhesive layer may be formed of TiN.
The semiconductor device according to the present invention may further include a barrier film interposed between the first portion of the contact stud and the intermetal insulating film. The barrier film may be formed of Ti/Tin.
The intermetal insulating film may be formed of an oxide film or formed to have a multi-layered structure of a silicon oxide film, a fluorinated silica glass (FSG) film, and a silicon oxide film that are sequentially deposited.
To achieve the second objective of the present invention, there is a provided a method of manufacturing a semiconductor device including multilevel interconnections as the first aspect of the present invention. In the method, a first metal interconnection layer is formed on a semiconductor substrate. Then, an intermetal insulating film is formed on the first metal interconnection layer. Next, a hard mask pattern having vertical sidewalls, which extend vertically with respect to the main surface of the semiconductor substrate, is formed on the intermetal insulating film in order to define an upper hole exposing a portion of the intermetal insulating film. Then, a via hole penetrating the intermetal insulating film is formed by etching a portion of the exposed intermetal insulating film. Next, a contact stud composed of a first portion filling the via hole and a second portion, which fills the upper hole and has vertical sidewalls that are extended vertically with respect to the main surface of the semiconductor substrate and an upper surface that is extended parallel to the main surface, is formed. Thereafter, the hard mask pattern is removed, and a second metal interconnection layer covering the vertical sidewalls and upper surface of the second portion of the contact stud is formed.
The hard mask pattern may be formed of a silicon nitride film.
When forming the contact stud comprises, a metal film entirely filling the via hole and the upper hole is formed and the metal film except for the portion filling the via hole and the upper hole is removed.
To remove the metal film, an etchback or chemical mechanical polishing (CMP) method can be used.
Removing the hard mask pattern includes exposing the vertical sidewalls of the second portion of the contact stud and can be performed by a wet etching method.
When forming the second metal interconnection layer, a metal film covering the vertical sidewalls and upper surface of the second portion of the contact stud are deposited, the metal film through a heat treatment is reflowed and the reflowed metal film is patterned.
The vertical sidewalls of the second portion of the contact stud are formed to face the vertical sidewalls of the hard mask pattern when forming the contact stud.
When forming the contact stud, a barrier film covering the inner walls of the via hole and the vertical sidewalls and upper surface of the hard mask pattern is formed, a metal film is formed to completely fill the via hole and upper hole that are defined by the barrier film, the barrier film that covers the upper surface of the hard mask pattern is exposed b
Cao Phat X.
Mills & Onello LLP
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