Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-10-26
2004-03-30
Le, Dinh T. (Department: 2811)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S536000, C327S589000, C365S201000
Reexamination Certificate
active
06714065
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device provided with a power supply circuit that generates an internal power supply voltage with a charge pumping operation.
2. Description of the Background Art
Currently, a burn-in test is conducted in a dynamic random access memory (DRAM) for the purposes of screening of a defective chip and evaluation of reliability. In a conventional burn-in test, such screening of the potential defective chip has been conducted by applying a high voltage to a chip operating in a high-temperature atmosphere to accelerate degradation of the defective portion.
In the generations on and after 0.25 &mgr;m, however, it has become impossible to apply a voltage high enough to allow thorough screening of defects in oxide films while a device after molding is in operation, because of the problem of reliability of a transistor including resistance to hot carrier. Therefore, it is common at present to perform the burn-in test in two stages, as a wafer level burn-in test and a regular burn-in test.
In the wafer level burn-in test, a defective chip potentially including a defect in the oxide film is screened by statically applying a stress voltage to the chip in the wafer state for a relatively short period of time, to accelerate elicitation of the defect. In the regular burn-in test being performed after molding, operational reliability is evaluated in the device level, by applying a high voltage in a high-temperature atmosphere over a long period of time.
In the DRAM, evaluation of the oxide film breakdown voltage is particularly necessary for a switching transistor of a memory cell and a switching transistor within a data line separating circuit, since a high gate-source voltage would be applied to these switching transistors.
FIG. 9
is a schematic diagram showing a configuration of a memory cell of a DRAM. In
FIG. 9
, one-element type DRAM cell is illustrated.
Referring to
FIG. 9
, the memory cell
10
includes a capacitor
11
storing data in the form of charges and a switching transistor
12
. The gate of switching transistor
12
is connected to a word line WL. In response to activation of word line WL, switching transistor
12
electrically connects a data line DL to one electrode (storage node) of capacitor
11
. The other electrode (cell plate electrode) of capacitor
11
is supplied with a cell plate voltage Vcp.
When word line WL is selected and set to an active state (high level), switching transistor
12
turns on, and the data stored in capacitor
11
is read out on data line DL.
Hereinafter, binary signal and voltage levels will be referred to as a high level and a low level, which will be expressed as “H level” and “L level”, respectively.
A boosted voltage VPP is employed as a voltage corresponding to the active state of word line WL, such that a sufficient signal voltage is read out to data line DL despite the influence of the threshold voltage of the switching transistor being an NMOS transistor.
Specifically, a gate-source voltage of at most a VPP level is applied to a gate oxide film of switching transistor
12
when turned on. This makes switching transistor
12
more susceptible to a defect than the other portions.
Thus, in the wafer level burn-in test, a static stress voltage (hereinafter, also simply referred to as “stress”) is applied to the oxide film of switching transistor
12
, while fixing the level of word line WL to the boosted voltage VPP, to screen a potential defect therein. The explanation above also applies to the switching transistor within the data line separating circuit.
FIG. 10
is a circuit diagram showing a configuration of the data line separating circuit.
Referring to
FIG. 10
, the data line separating circuit
20
is arranged to allow a sense amplifier to be shared by bit lines placed on its either side, for reduction of a chip area.
Data line separating circuit
20
includes a sense amplifier
21
and switching transistors
23
-
28
.
Sense amplifier
21
is shared by bit line pairs BLPL and BLPR located at its respective sides, and amplifies a voltage difference between sense nodes Ns and /Ns. Bit line pair BLPL includes bit lines BLL and /BLL for transmission of data complementary to each other. Likewise, bit line pair BLPR includes bit lines BLR and /BLR for transmission of data complementary to each other.
Switching transistor
23
is electrically connected between bit line BLL and sense node Ns. Switching transistor
24
is electrically connected between bit line /BLL and sense node /Ns. Switching transistor
25
is electrically connected between bit line BLR and sense node Ns, and switching transistor
26
is electrically connected between bit line /BLR and sense node /Ns.
Switching transistors
23
and
24
have their gates receiving a control signal BLIL that is activated to an H level when the bit line pair on the left side is selected. Likewise, switching transistors
25
and
26
have their gates receiving a control signal BLIR activated to an H level when the bit line pair on the right side is selected.
Data line separating circuit
20
further includes switching transistors
27
and
28
for connecting sense nodes Ns and /Ns to a data input/output line pair DIOP.
Switching transistor
27
is electrically connected between sense node Ns and a line DIO that is one of the complementary data input/output lines constituting the data input/output line pair DIOP. Switching transistor
28
is electrically connected between sense node /Ns and a line /DIO that is the other of the complementary data input/output lines. Switching transistors
27
and
28
have their gates receiving a control signal CS that is activated to an H level according to a result of column selection.
In such a data line separating circuit, a voltage of the boosted voltage VPP level is applied to the gates of switching transistors
23
-
28
such that the data of an H level can be read/written with respect to the bit lines or the data input/output lines at a sufficient signal voltage. Specifically, control signals BLIL, BLIR and CS are each set to the boosted voltage VPP at the time of an H level (of an active state).
Accordingly, a gate-source voltage of at most the VPP level is applied to the gate oxide films of switching transistors
23
-
28
. Thus, in the wafer level burn-in test, it is necessary to conduct screening of potential defects of switching transistors
23
-
28
, as in the case of the switching transistor within the memory cell, by applying constant stress to the oxide films thereof.
Boosted voltage VPP used as the ON voltage of these switching transistors is usually generated by a boosting circuit with a charge pumping operation.
FIG. 11
is a circuit diagram showing a configuration of a common boosting circuit as an example of the power supply circuit conducting the charge pumping operation. Shown in
FIG. 11
is a so-called single boost type boosting circuit.
Referring to
FIG. 11
, the boosting circuit
30
includes a ring oscillator
31
, N channel MOS transistors
32
-
35
, MOS capacitors
36
-
38
, and a clock transmission circuit
40
. Clock transmission circuit
40
includes inverters
41
-
47
. Hereinafter, N channel MOS transistor and P channel MOS transistor will be simply referred to as “NMOS transistor” and “PMOS transistor”, respectively.
Ring oscillator
31
generates a pump clock PCLK having constant periods to a node N
1
. Inverters
43
and
47
transmit pump clock PCLK in phase to a node N
2
. Inverters
42
and
46
transmit pump clock PCLK in phase to a node N
3
. Inverters
41
,
44
and
45
transmit pump clock PCLK in opposite phase to a node N
4
.
MOS capacitor
36
is coupled between nodes N
2
and N
5
. MOS capacitor
37
is coupled between nodes N
3
and N
6
. MOS capacitor
38
is coupled between nodes N
4
and N
7
. MOS capacitors
36
-
38
are used to conduct the charge pumping operation.
NMOS transistor
35
is electrically connected between a power supply voltage VDD and node N
7
Komiya Yuichiro
Mitsui Katsuyoshi
Le Dinh T.
McDermott & Will & Emery
Renesas Technology Corp.
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