High value polysilicon resistor

Details High value polysilicon resistor High value polysilicon resistor

2002-08-22

2004-03-02

Easthom, Karl D. (Department: 2832)

Electrical resistors

With base extending along resistance element

Resistance element coated on base

C257S538000, C438S210000, C438S330000

Reexamination Certificate

active

06700474

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and process for forming polysilicon resistors on semiconductor substrates, and more particularly to dual layer polysilicon high value resistor structures.
2. Background Information
Forming high value polysilicon resistors on the same wafer together with other circuit components can be difficult. One reason is that the thickness of the polysilicon layer or layers is determined by the required characteristics of the other devices. For example, the deposited polysilicon must also form the gates and/or emitters of active components, lower value resistors and capacitor plates. This requires thicknesses that are typically greater than 200 nanometers (nm).
Polysilicon resistivity is a non-linear function of doping where the resistivity decreases quickly as the doping dose increases. Implant dose control makes resistivity greater than about 0.060 ohm-cm difficult to achieve. Since the resistance is a function of the resistivity divided by the thickness, practical sheet resistances are limited to not much above 2000 ohms/square. Therefore, meg-ohm resistors will consume much space and will greatly increase die size.
Attempts to form high value polysilicon resistors have used ion implants and reduced polysilicon thicknesses with limited success. Other structures have used multiple layers of polysilicon. But, these often require many additional steps and processes beyond those needed for the core devices on the same wafer, and the resulting resistors have device and process control limitations.
One such attempt is described in U.S. Pat. No. 6,211,031 to Dah-Chih Lin et al. This invention describes a split or dual value polysilicon process using two layers. A first layer is deposited and patterned to expose the underlying dielectric substrate. A second polysilicon layer is deposited over the first layer and the dielectric. Dual parallel resistors are formed. If the polysilicon resistivity is too high, the resistor end contact structures will form rectifying contacts. There is no suggestion or disclosure of processing to provide low ohmic end structures. The process of etching a contact hole that terminates on but does not go through the thin poly layer is also difficult.
Another approach is found in U.S. Pat. No. 6,054,359 to Yu-Ming Tsui et al. This patent describes a thin polysilicon layer with a thicker polysilicon layer overlaying the thinner layer. The thin layer is doped in place and the thicker layer is undoped. The combination of the two layers forms the resistor. This particular invention suffers especially from the undoped layer forming part of the end structures of the resistors being formed. The result is a relatively high ohmic end contacts for the resistors.
Prior art does not address the technical problems of integrating silicide or metal contacts into thin polysilicon resistors. In the case of silicide, the forming reaction will consume much if not all of a thin poly layer. For contact etch, the required overetch can completely burrow through the poly. Each of these can make the resistor non-functional or unreliable. For these reasons, prior art techniques often are forced to accept high impedance end structures or even non-ohmic connections.
Therefore, a need remains to provide high value polysilicon integrated circuit resistors having existing process compatibility; with few, if any, added process steps; and with a well controlled of the resistor end structures having relatively low ohmic resistances to the metalization layer.
SUMMARY OF THE INVENTION
An objective of the present invention is the creation of a high value polysilicon resistor that is easily integrated into an existing CMOS, bipolar, or BiCMOS process flow. This can be done either with no additional process complexity, or by the addition of a small number of dedicated processing steps, depending on the core flow being used.
A second objective of the invention is construction of the high value resistor out of two separately deposited polysilicon layers in such a way that the intrinsic resistor is formed from only one layer, while the resistor ends are formed from two self-aligned stacked layers. This allows the intrinsic resistor to be thinner and more lightly doped to achieve a high sheet resistance value (greater than 2000 ohms per square), while the end polysilicon stack can be thick enough to easily withstand normal processing such as contact etch, silicide formation, or other existing steps. The ends can also be implanted or otherwise doped heavier than the resistor body so that ohmic connections between the poly and the silicide or contact material can be achieved.
A third objective of the invention is formation of the resistor body with the second of the two polysilicon depositions and the formation of the resistor ends with both the first and second polysilicon depositions. This scheme of using the second polysilicon deposition to form the resistor body allows the resistor to be added to an existing process flow with little or in some cases no additional processing.
The above objectives are addressed in the present invention that provides two layers of polysilicon using a split poly approach. The intrinsic resistor is formed out of only one, thin, layer that can be constructed with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant or by insitu doping methods. This layer may be a new, dedicated process step, or may be part of an existing processing sequence such as the non-selective epi (silicon or SiGe) and poly deposition in an epi base BiCMOS flow. The resistor ends, however, are comprised of two layers of polysilicon. The top layer is the intrinsic resistor layer, while the bottom layer is added for the resistor ends, and self-aligned to the first layer during a poly etching step. These ends are thick enough so that standard silicide and contact etch processing may be added to the structure without special precaution. The bottom resistor end layer is typically a polysilicon layer already in the process flow. In addition, already available implants may be incorporated into the resistor ends to ensure ohmic contacts are achieved. These steps can provide consistent, low resistance, ohmic end contacts with sufficient thickness for the required contact overetch.


REFERENCES:
patent: 4528582 (1985-07-01), Cohen et al.
patent: 4785342 (1988-11-01), Yamanaka et al.
patent: 5793097 (1998-08-01), Shimamoto et al.
patent: 5959343 (1999-09-01), Harada et al.
patent: 6054359 (2000-04-01), Tsui et al.
patent: 6211031 (2001-04-01), Lin et al.

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