Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-01-14
2004-11-02
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S148000, C331SDIG002, C375S376000
Reexamination Certificate
active
06812754
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a clock synchronizer, and particularly, to a clock synchronizer generating a second clock signal synchronized with a first clock signal.
BACKGROUND ART
Conventionally, a semiconductor integrated circuit device is provided with a PLL (Phase Locked Loop) circuit generating an internal clock signal in synchronization with an external clock signal in order to synchronize the outside and the inside of a chip.
FIG. 23
is a circuit block diagram showing the configuration of such a PLL circuit. In
FIG. 23
, the PLL circuit includes a phase comparator
121
, a charge pump circuit
122
, a loop filter
127
, a voltage control oscillator (hereinafter referred to as VCO)
130
, and a frequency divider
131
.
An external clock signal is input into phase comparator
121
as a reference clock signal RCLK. Phase comparator
121
compares the phase of reference clock signal RCLK and that of a feedback clock signal FCLK, and outputs signals UP, DOWN based on the comparison result. When the phase of clock signal FCLK is advanced with respect to the phase of reference clock signal RCLK, signal DOWN is raised to an activated level of “H” level for a time period corresponding to a phase difference, and when the phase of clock signal FCLK is delayed with respect to the phase of reference clock signal RCLK, signal UP is lowered to an activated level of “L” level for a time period corresponding to a phase difference. When there is no difference in the phases of clock signals FCLK and RCLK, signals DOWN, UP are set to be at “H” level and “L” level, respectively, in a pulsive manner.
Charge pump circuit
122
includes a P-channel MOS transistor
123
and a switching element
124
connected in series between the line of a power-supply potential VCC and a node N
122
; and a switching element
125
and an N-channel MOS transistor
126
connected in series between node N
122
and the line of a ground potential GND.
The gate of P-channel MOS transistor
123
is supplied with a constant bias potential VBP, whereas the gate of N-channel MOS transistor
126
is supplied with a constant bias potential VBN. Each of MOS transistors
123
,
126
constitutes a constant-current source. Switching element
124
conducts for a period during which signal UP is at the activated level of “L” level. Switching element
125
conducts for a period during which signal DOWN is at the activated level of “H” level.
Loop filter
127
includes a resistance element
128
and a capacitor
129
connected in series between node N
122
and ground potential GND. Capacitor
129
is charged and discharged by charge pump circuit
122
. The voltage of node N
122
is supplied to VCO
130
as a control voltage VC.
VCO
130
outputs an internal dock signal CLK having a frequency corresponding to control voltage VC. Internal clock signal CLK is applied to an internal circuit of the semiconductor integrated circuit device and also to frequency divider
131
. Frequency divider
131
divides the frequency of clock signal CLK by N (wherein N is a positive integer) to generate clock signal FCLK. Clock signal FCLK is returned to phase comparator
121
.
Control voltage VC is adjusted such that the frequencies and phases of clock signals RCLK and FCLK agree with each other, and then the frequencies and phases of clock signals RCLK and FCLK agree with each other, resulting in a lock state. In the locked state, internal clock signal CLK has a frequency N times as high as that of external clock signal RCLK and is a signal synchronizing with external clock signal RCLK. The internal circuit of the semiconductor integrated circuit device operates in synchronization with internal clock signal CLK. Therefore, the outside and the inside of the chip can be synchronized.
However, the conventional PLL circuit had problems as described below.
Now, a case is considered where reference clock signal RCLK and feedback clock signal FCLK agree in phase. In this case, signal UP is lowered to “L” level in a pulsive manner for a certain period of time with the same cycle as that of dock signals RCLK, FCLK. Likewise, signal DOWN is raised to “H” level in a pulsive manner for the same period of time and with the same cycle as that of signal UP. The reason why signals UP, DOWN are set to be at “L” level and “H” level in a pulsive manner even though clock signals RCLK and FCLK agree in phase with each other is to avoid a dead band being created.
At this moment, if current Ic flowing through P-channel MOS transistor
123
is the same as current Id flowing through N-channel MOS transistor
126
, signals UP and DOWN will have the same pulse width, so that the exactly same amount of charge is charged and discharged without the amount of charge in capacitor
129
of loop filter
127
changed. Thus, no change occurs in control voltage VC, and VCO
130
keeps outputting clock signal CLK having the same frequency X (Hz). As a result, the PLL circuit will be in the locked state in a state having no phase difference between clock signals RCLK and FCLK.
However, when there is no agreement between charging current Ic and discharging current Id, the locked state cannot be obtained in the state having no phase difference between clock signals RCLK and FCLK. For example, considering the case where charging current Ic is larger than discharging current Id, if signals UP and DOWN have the same pulse width, the amount of charge that is charged by charging current Ic will be unequal to the amount of charge that is discharged by discharging current Id. To equalize these amount of charges, the pulse width of signal DOWN must be made larger than the pulse width of signal UP.
Then, the state where the pulse width of signal DOWN is larger than the pulse width of signal UP means a state where the phase of feedback clock signal FCLK is delayed with respect to the phase of reference clock signal RCLK, and the PLL circuit is locked in this state. This generates a steady phase difference, i.e. an offset, between clock signals RCLK and FCLK. Same applies to the case where discharging current Id is larger than charging current Ic. In sum, in the PLL circuit, if there is no agreement in magnitude between charging current Ic and discharging current Id, an offset will occur.
Next, a case is considered where charging current Ic and discharging current Id disagree with each other in magnitude. In designing of the PLL circuit, assuming that the operating frequency of the PLL circuit is X (Hz), VCO
130
obtains a control voltage Y (V) oscillated at X (Hz), and the sizes of MOS transistors
123
,
126
and the levels of bias potentials VBP, VBN are determined such that charging current Ic and discharging current Id are equal to each other when control voltage VC is Y (V). Therefore, when the PLL circuit operates as designed, charging current Ic and discharging current Id are equal to each other, and hence the locked state is attained in the state having no phase difference between clock signals RCLK and FCLK.
However, due to variations of a manufacturing process, an environment temperature and power-supply voltage VCC, control voltage VC at the time when output clock signal CLK of VCO
130
attains to X (Hz) is easily varied from Y (V). Moreover, when the PLL circuit is operated at a frequency other than X (Hz), control voltage VC in the locked state is a value different from Y (V). Therefore, in such cases, charging current Ic and discharging current Id are unequal, and an offset occurs.
Disclosure of the Invention
Therefore, a main object of the present invention is to provide a clock synchronizer capable of inhibiting occurrence of an offset.
An object of the present invention can be achieved by providing a clock synchronizer generating a second clock signal synchronized with a first clock signal, including a phase difference detection circuit detecting a phase difference between the first and second dock signals, and setting a first control signal to be at an activated level for a time period corresponding to the phase difference; a loop filter connected to a pr
McDermott & Will & Emery
Nguyen Minh
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