Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-11
2004-08-24
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
Reexamination Certificate
active
06781884
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly, to a system for setting voltage thresholds of memory cells in a memory device.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as memory devices, are commonly used as information storage devices in digital systems. As the amount of information that needs to be stored increases, it has become increasingly important to have an efficient way of accessing such memory devices.
Generally, memory read or write operations are initiated in response to external signals provided to the memory by a controller, such as a processor. In most cases, the amount of information that needs to be transferred during a memory access is large. In addition, the rate at which the information is propagated from a processor to a memory device and vice versa continues to increase. Therefore, increasing performance demands are being placed on the ability to read and write information to memory devices.
In a FLASH memory device, multiple core cells are programmed simultaneously. Since the core cells are in the same word, the programmed voltage thresholds (Vth) are generally the same from cell to cell. However, there are several cases where it is desirable to set the programmed Vth individually for each cell. One way to do this is to program the cells one by one while changing the programming conditions and program verify levels for each cell. Unfortunately, this type of individual programming takes excessive amounts of time to complete the programming of all core cells.
Therefore, it would be desirable to have a way to quickly program core cells to set individual Vth levels for each cell in a memory device.
SUMMARY OF THE INVENTION
The present invention includes a system for setting voltage thresholds in a memory device. The system operates by selectively enabling and disabling programming pulses for all memory cells associated with a selected word line. Thus, the system achieves fast programming times since the memory cells are programmed in parallel, and it is possible to obtain desired voltage thresholds for the programmed cells.
In one embodiment of the present invention, apparatus is provided to set voltage threshold levels of a plurality of memory cells in a memory device. The plurality of memory cells are coupled to a common word line. The apparatus includes a plurality of gates that are coupled between a voltage source and the plurality of memory cells, the gates include control inputs that receive control signals that open and close each gate, so that when a selected gate is closed, the voltage source is coupled to a selected memory cell and when the selected gate is open the current source is uncoupled from the selected memory cell. The apparatus also includes control logic that generates the control signals to open and close the gates to individually enable and disable programming of the voltage threshold of each of the memory cells.
In another embodiment of the present invention, a method is provided for setting voltage threshold levels of a plurality of memory cells in a memory device. The plurality of memory cells are coupled to a common word line. The method includes the steps of gating a voltage source to the plurality of memory cells to enable programming of the plurality of memory cells, programming the enabled memory cells, verifying that at least a portion of the plurality of memory cells are programmed with a correct voltage threshold, disabling the voltage source to the at least a portion of the plurality of memory cells, and repeating the steps programming, verifying and disabling until all of the plurality of memory cells are programmed with the correct voltage threshold.
REFERENCES:
patent: 5798966 (1998-08-01), Keeney
patent: 6344999 (2002-02-01), Iwahashi
Fujitsu Limited
Le Thong Q.
Sheppard Mullin Richter & Hampton LLP
LandOfFree
System for setting memory voltage threshold does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System for setting memory voltage threshold, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for setting memory voltage threshold will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3285102