Data realignment techniques for serial-to-parallel conversion

Details Data realignment techniques for serial-to-parallel conversion Data realignment techniques for serial-to-parallel conversion

2002-10-10

2004-03-16

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C712S204000

Reexamination Certificate

active

06707399

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to data realignment in serial-to-parallel converters, and more particularly, to techniques for realigning the boundary between data bytes when converting serial data to parallel data.
A serial-to-parallel converter circuit is used to convert a serial data stream into a parallel data stream. Bits of data are shifted into a shift register from a single input data stream. The data bits stored in the register are then simultaneously shifted out of the register along parallel signal lines as parallel data. Each data bit is output on a separate parallel signal line. The data bits are shifted out of the register as bytes of data (e.g., 8 bits each). Thus, the registers groups serial data bits into data bytes on parallel signal lines.
The register determines the boundary between one data byte and the next data byte. Typically, when serial data is converting to parallel data, the boundary between data bytes is determined randomly, depending upon when the data transmitting and receiving devices power up.
Therefore, it would be desirable to provide techniques to realign the boundary between output data bytes from a serial-to-parallel data converter to match a preset data boundary.
BRIEF SUMMARY OF THE INVENTION
The present invention includes techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter. Bits of serial data are shifted into a first register. A first clock signal controls the shifting of data into the first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary.
A load enable signal controls the loading of parallel data into the second register. The boundary between the parallel data bytes can be realigned using the load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits.
The parallel data is then loaded from the second register into a third register. A second load signal controls the loading of data into the third register. The phase of the second load signal is fixed relative to a second clock signal. The second clock signal controls the circuitry that receives the parallel data output of the third register. The parallel data output of the third register is synchronized to the second clock signal to ensure enough set up and hold time for the data signals output by the third register.


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patent: 5862367 (1999-01-01), Chiao-Yen
patent: 6252527 (2001-06-01), Yang

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