Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2002-10-08
2004-12-07
Pert, Evan (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C174S262000, C174S263000, C361S760000, C361S779000, C361S803000, C257S778000
Reexamination Certificate
active
06828512
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electrical assemblies and, more particularly, to substrate and methods for providing via-in-pad electrical interconnects to facilitate high-performance and high-density component interconnection.
BACKGROUND OF INVENTION
It is common that electrical assemblies comprise at least one substrate that is used as a structural platform as well as to electrically interconnect one electrical component with another. The substrate is commonly a relatively rigid panel that comprises a variety of electrical interconnects that run through, within, and/or upon the panel. Examples of substrates include, but are not limited to, printed circuit boards (PCB), motherboards, and carrier substrates within microelectronic packages.
One long-standing method of attachment of an electrical component to the substrate is the well established process of providing the substrate with metalized through-bores, referred to as vias, through which corresponding pins on the electrical component are inserted, and subsequently soldered from the opposite side of the substrate. Through-bore vias are the most economical via type from a substrate manufacturing perspective. With the advent of new manufacturing technologies that do away with the pins on the electrical component, there have been attempts to continue to use the relatively inexpensive through-bore via substrates with these pin-less components.
One method of interconnecting electrical components to the substrate, or one substrate to another substrate, incorporates surface mount technology (SMT). The SMT electrical component replaces the pin or wire contacts with simple, flat electrical interconnect known as land pads. Surface mount technology electrical components are widely used because of their compact size and simplicity of interconnection doing away with such issues as pin alignment and bulkiness. Examples of SMT electrical components include, but are not limited to, flip chip-ball grid array (FC-BGA) packaging and chip-scale packaging.
FIG. 1
is a cross-sectional view of a VIP substrate
10
which comprises a type of electrical interconnect known in the art as a via-in-pad (VIP)
20
. The VIP
20
is a modification of the standard through-bore via substrate. As is with the standard through-bore via substrate, the VIP
20
is a through-bore
16
extending through the thickness of a substrate core
18
with an electrically conductive liner
21
forming a VIP bore
22
.
FIG. 2
is a perspective view of the electrically conductive liner
21
shown without the substrate core
18
for clarity. In addition, the electrically conductive liner
21
also forms a first and second VIP bond pad
24
,
26
adjacent the through-bore
16
on a portion
13
of a first substrate surface
12
of the VIP substrate
10
. The VIP bore
22
is also referred to as a via, hence the designation “via-in-pad”.
With SMT electrical interconnect
9
replacing the pins, electrical components
8
require an electrical interconnect on the surface of the VIP substrate
10
that has sufficient surface area to provide for a satisfactory electrical interconnection. The first and second VIP bond pads
24
,
26
provide an expanded conductive contact surface to permit interconnection with the SMT electrical interconnect
9
using a reflowable electrically conductive interconnect material
28
. Hence, the VIP bore
22
is not used and merely remains as a by-product of the established substrate manufacturing process.
The SMT electrical component-to-substrate interconnection is made using a reflow technique, for example, among others, the controlled collapse chip connection (C4) process. The C4 process is extensively used to interconnect a microelectronic die to a carrier substrate, but is equally applicable to other electrical component-to-substrate interconnection.
The C4 process involves providing reflowable electrically conductive interconnect material
28
on each SMT electrical interconnect
9
. The electrical component
8
is positioned on top of the VIP substrate
10
such that the reflowable electrically conductive interconnect material
28
is in contact with the respective upwardly-facing first VIP bond pads
24
. The assembly is processed at elevated temperature wherein the reflowable electrically conductive interconnect material
28
softens and/or melts to form an integral bond with the SMT electrical interconnects
9
and the first VIP bond pads
24
. Upon cooling, the reflowable electrically conductive interconnect material
28
solidifies providing an electrical interconnection between the electrical component
8
and the VIP substrate
10
.
The electrical interconnection between the SMT electrical interconnects
9
and the first VIP bond pads
24
is not without complications. One such complication is the migration of the molten reflowable electrically conductive interconnect material
28
into the VIP bore
22
by capillary action. If a sufficient amount of reflowable electrically conductive interconnect material
28
is drawn away from the first VIP bond pad
24
and into the VIP bore
22
, there will be insufficient reflowable electrically conductive interconnect material
28
to make a proper interconnection.
One process that has been tried in the art to limit the amount of reflowable electrically conductive interconnect material
28
migrating into the VIP bore
22
involved plugging it with a soldermask plug
29
. Soldermask material is deposited into the VIP bore
22
from the opposite side of the VIP substrate
10
intended to be interconnected. The soldermask plug
29
limits the amount of reflowable electrically conductive interconnect material
28
that can flow into the VIP bore
22
, as well as blocks the flow out of the other side of the VIP bore
22
.
The practice of plugging the opposite end of a VIP bore
22
creates additional problems effecting the electrical interconnection. As the reflowable electrically conductive interconnect material
28
is being heated to its melting point during the reflow process, volatiles in the soldermask material will reach their vapor point and be released as gasses. The expanding gasses can migrate into the molten reflowable electrically conductive interconnect material
28
causing a ballooning effect which may produce a weak or failed interconnection. Further, the ballooned reflowable electrically conductive interconnect material
28
may possibly make contact with adjacent VIPs
20
causing an electrical short.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for a substrate and a method for interconnecting electrical components to a substrate comprising VIP interconnects that offers relatively high density while providing a relatively high quality interconnection.
REFERENCES:
patent: 5275330 (1994-01-01), Isaacs et al.
patent: 5656798 (1997-08-01), Kubo et al.
patent: 5734560 (1998-03-01), Kamperman et al.
patent: 6076726 (2000-06-01), Hoffmeyer et al.
patent: 6199273 (2001-03-01), Kubo et al.
patent: 6252779 (2001-06-01), Pierson et al.
patent: 6300578 (2001-10-01), Hoffmeyer et al.
patent: 6444924 (2002-09-01), Ishida et al.
patent: 6583517 (2003-06-01), Jimarez
Chan Sook Chien
Chung C. Key
Leong Kum Foo
Intel Corporation
Schwabe Williamson & Wyatt P.C.
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