Electrolysis: processes – compositions used therein – and methods – Electrolytic erosion of a workpiece for shape or surface... – With mechanical abrasion or grinding
Reexamination Certificate
2002-01-11
2004-10-12
Nicolas, Wesley A. (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic erosion of a workpiece for shape or surface...
With mechanical abrasion or grinding
C205S663000, C205S668000, C205S087000, C205S222000, C205S205000, C204S212000, C204S22400M, C204S275100
Reexamination Certificate
active
06802955
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to techniques for depositing conductive material and/or for removing conductive material from a workpiece such as a semiconductor wafer. More particularly, this invention relates to an apparatus, a system, and a method for electrolytically depositing and/or planarizing a conductive material on a workpiece surface and polishing the surface of the workpiece to remove a portion of the conductive material. Still more particularly, this invention relates to the deposition and/or planarization of copper on a workpiece surface.
BACKGROUND OF THE INVENTION
Chemical mechanical polishing (CMP) is a technique which has been conventionally used for the planarization of semiconductor wafers. For example, see U.S. Pat. No. 5,099,614, issued in March in 1992 to Riarai et al; U.S. Pat. No. 5,329,732 issued July 1994 to Karlsrud et al, and U.S. Pat. No. 5,498,199 issued March 1966 to Karlsrud et al. Furthermore, chemical mechanical polishing is often used in the formation of microelectriconic devices to provide a substantially smooth, planar surface suitable for subsequent fabrication processes such as photoresist coating and pattern definition. A typical chemical mechanical polishing apparatus suitable for planarizing a semiconductor surface generally includes a wafer carrier configured to support, guide, and apply pressure to a wafer during the polishing process, a polishing compound such as a slurry to assist in the removal of material from the surface of the wafer, and a polishing surface such as a polishing pad. In addition, the polishing apparatus may include an integrated wafer cleaning system and/or an automated load/unload station to facilitate automatic processing of the wafers.
A wafer surface is generally polished by moving the surface of the wafer to be polished relative to the polishing surface in the presence of a polishing compound. In particular, the wafer is placed in a carrier such that the surface to be polished is placed in contact with the polishing surface, and the polishing surface and the wafer are moved relative to each other while slurry is supplied to the polishing surface.
Chemical mechanical polishing may also be used to form microelectronic features. For example, a conductive feature such as a metal line, conductive plug, or the like may be formed on a surface of a wafer by forming trenches and vias on the wafer surface, depositing conductive material over the wafer surface and into the trenches and vias, and removing the conductive material on the surface of the wafer using chemical mechanical polishing, leaving the vias and trenches filled with conductive material. The conductive features often include a barrier material to reduce unwanted diffusion of the conductive material and to promote adhesion between the conductive material and any adjacent layer of the circuit.
Aluminum is often used to form conductive features because its characteristics are compatible with conventional deposition (e.g. chemical vapor deposition) and etch (e.g., reactive ion etch) techniques. While the use of aluminum to form conductive features is adequate in some cases, the use of aluminum in the formation of conductive features becomes increasingly problematic as the size of the conductive feature decreases. In particular, as the size of the conductive feature decreases, the current density through the feature generally increases, and thus the feature becomes increasingly susceptible to electromigrations; i.e., the mass transport of metal due to the flow of current. Electromigration may cause short circuits where the metal accumulates, open circuits where the metal has been depleted, and/or other circuit failures. Similarly, increased conductive feature resistance may cause unwanted device problems such as access power consumption and heat generation.
Recently, techniques have been developed which utilize copper to form conductive features because copper is less susceptible to electromigration and exhibits a lower resistivity than aluminum. Since copper does not readily form volatile or soluble compounds, the copper conductive features are often formed using damascene. More particularly, the copper conductive features are formed by creating a via within an insulating material, depositing a barrier layer onto the surface of the insulating material and into the via, depositing a seed layer of copper into the barrier layer, electrodepositing a copper layer onto the seed layer to fill the via, and removing any excess barrier metal and copper from the surface of the insulating material using chemical and mechanical polishing. During the electrodeposition process, additives such as leveling agents may be added to the plating bath to reduce the formation of voids within the conductive features.
Forming copper conductive features according to the method described above can be relatively expensive, in part because each material deposition and removal step is typically carried out using dedicated equipment. U.S. Pat. No. 6,176,922, issued to Talieh on Jan. 23, 2001, discloses an apparatus for both electroplating and polishing copper. The apparatus disclosed includes a wafer carrier having a cathode electrode contact that contacts the surface of the wafer to be polished. Unfortunately, the apparatus shown in Taleih is problematic is several ways. In particular, a film deposited using the apparatus of Taleih may be undesirably non-uniform because the cathode electrode contacts the wafer in a limited number of fixed locations about the perimeter of the wafer. Such a cathode contact configuration may lead to increased deposition about the perimeter of the wafer, i.e., in the areas proximate to the cathode contact, and thus lead to non-uniform deposition of the conduct film. Furthermore, wafer areas in contact with the cathode generally cannot include active devices.
As stated previously, the CMP machine typically includes a wafer carrier configured to hold, rotate, and transport a wafer during the process of polishing or planarizing the wafer. During the planarizing operation, a pressure applying element (e.g., a rigid plate, a bladder assembly, or the like) that may be an integral part of the wafer carrier, applies pressure such that the wafer engages a polishing surface with a desired amount of force. The carrier and the polishing surface are rotated, typically at different rotational velocities, to cause relative lateral motion between the polishing surface and the wafer and to promote uniformed planarization. The polishing surface generally comprises a horizontal polishing pad that may be formed of various materials such as blown polyurethane and are available commercially from, for example, Rodel Inc. located in Phoenix, Ariz. An abrasive slurry may also be applied to the polishing surface which acts to chemically weaken the molecular bonds at the wafer surface so that the mechanical action of the polishing pad and slurry abrasive can remove the undesirable material from the wafer surface.
Unfortunately, the CMP process tends to leave stresses in the worked workpiece leading to subsequent cracking and shorting between metal layers. Furthermore, the CMP process may result in sheering or crushing of fragile layers. This process also has a tendency to cause dishing in the center of wide metal features, such as trenches and vias, oxide erosion between metal features, and dielectric oxide loss. Electrochemical planarization is an attractive alternative to CMP because it does not impart significant mechanical stresses to the workpiece, and consequently does not significantly reduce the integrity of the devices. Furthermore, electrochemical planarization is less likely to cause dishing, oxide erosion, and oxide loss of the dielectric layer.
Electrochemical planarization is based on electroetching and electrochemical machining; that is, the removal of a thin layer of metal from a substrate through the action of an electrical solution and electricity. For example, if two electrodes, an anode and a cathode, are emerged in a liquid electrolyte and are w
Emesh Ismail
Gopalan Periya
Palmer Bentley J.
Rayer, II Phillip M.
Ingrassia Fisher & Lorenz PC
Nicolas Wesley A.
Speedfam-Ipec Corporation
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