Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-02-28
2004-12-07
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06828213
ABSTRACT:
FIELD OF INVENTION
This invention relates generally to semiconductor devices and more particularly to method of forming shallow trench isolation (STI) structures and to side wall nitride formation in shallow trench isolation to provide a more uniform STI oxide liner and to also make a moat nitride pullback possible.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor devices, isolation structures are formed between active areas in which electrical devices such as transistors, memory cells, or the like, are to be formed. The isolation structures are typically formed during initial processing of a semiconductor substrate, prior to the formation of such electrical devices. Typical isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) processes, by which isolation structures are formed between active regions of a semiconductor device. As semiconductor device dimensions have been reduced over the past several years, limitations on the scalability of and other problems associated with LOCOS isolation techniques, have resulted in a general trend away from LOCOS techniques and an increase in the use of STI techniques, particular in modem, high device density applications.
STI isolation techniques involve the formation of shallow trenches in the isolation areas or regions of a semiconductor wafer, which are subsequently filled with dielectric material such as silicon dioxide (Si02) to provide electrical isolation between devices subsequently formed in the active regions on either side of the filled trenches. A pad oxide layer and a nitride layer are typically formed over the substrate surface and patterned to expose only the isolation regions, with the prospective active device regions covered. The nitride layer operates as a hard mask during subsequent processing steps, and the pad oxide layer functions to relieve stress between the underlying silicon substrate and the nitride layer. An anisotropic (e.g., “dry”) etch is then performed to form a trench through the nitride, pad oxide, and substrate. Once the trench is etched, dielectric material is deposited to fill the trench with oxide. Thereafter, the device is commonly planarized using a chemical mechanical polishing (CMP) process and the nitride protection layer is removed.
A conventional STI process is illustrated in
FIGS. 1-7
to form trench isolation structures in a semiconductor device
12
. In
FIG. 1
, a thermal oxidation process is used to grow a pad oxide layer
14
over a semiconductor substrate
16
. A nitride layer
18
, such as Si3N4 is then deposited in
FIG. 2
, such as by low pressure chemical vapor deposition (LPCVD). The nitride layer
18
is used to protect the active regions of the substrate
16
from adverse effects of the subsequent formation of isolation trenches between the active regions. The active regions of the device
12
are then masked in
FIG. 3
using a patterned etch mask
20
, leaving the isolation region of the nitride layer
18
exposed. A dry etch
22
is performed to form a trench
24
through the nitride layer
18
, the pad oxide layer
14
, and into the substrate
16
. The active mask
20
is then removed in FIG.
4
and an oxide liner
26
is formed in the trench
24
to remove or repair substrate damage caused by the trench etch process
22
.
Once the trench
24
and the liner
26
are formed, a dielectric material
28
is deposited in
FIG. 5
via a deposition process
30
to fill the trench
24
and also to coverthe nitride layer
18
in the active regions of the device
12
. In
FIG. 6
, a chemical mechanical polishing (CMP) process
32
is used to planarize the upper surface of the device
12
, which exposes the remainder of the nitride layer
18
. Following planarization, the nitride layer
18
is removed via an etch process
34
in
FIG. 7
to complete the isolation process. However, in conventional isolation processing, sharp comers in the isolation trench can cause various problems with the operation performance of transistors and other devices fabricated in the adjacent active regions of the device
12
.
STI (Shallow Trench Isolation) is the solution for transistor isolations at quarter micron (and below) technology. In today's integrated circuit (IC) technology most products are trying to use STI as an isolation approach with much smaller dimensions/pitch where this is facing a limitation of STI gap fill in conjunction with the STI liner oxidation.
Presently with the small STI dimensions, it is getting more difficult to fill the STI trenches without any voids. Of course the main problem is the narrow STI width where in conjunction with bottle necking of the STI oxide liner it will make the filling difficult. The bottle necking of the STI liner oxidation is due to the oxide growth rate on the STI walls that have different plane orientation than the <001>. As it is seen in
FIG. 8
, oxide liner grown on the 87 deg walls is about 2-3 times of the intended oxidation thickness where it is about 50% of the intended thickness at the bottom of the STI.
On the other hand, the STI oxide recess at moat comers are known to cause problems for inverse narrow width effect. The STI oxide loss is due to the subsequent oxide deglazes in the process post STI fill and CMP where in effect the STI oxide will recess below the silicon surface. When the poly-silicon is deposited and etched to form the gate of a transistor, there will be a sharp moat comer under the gate poly as it is seen in FIG.
9
.
Also in this figure it is shown the STI gap fill void
91
which was mentioned above. It is well known in the industry that the STI oxide recess can be avoided if the moat nitride was pulled back (etched with hot phosphoric acid) prior to the STI gap fill. But this approach has its own problems when it is integrated with the STI nitride liner. This STI nitride liner is needed for stress reduction in the STI. But if the STI nitride liner is present in the process, unintentionally a part of this nitride liner will be deglazed during the moat nitride removal. This is a problem where finally poly will be deposited in the void which was left behind after nitride liner was deglazed.
SUMMARY OF INVENTION
In accordance with one embodiment of the present invention:
1) A method to reduce oxide growth on STI walls is provided by depositing and etching a nitride liner to create a thin side wall prior to the STI liner oxidation.
2) A method to make the moat nitride pull back process possible in the present of the STI nitride liner process for STI stress reduction is provided by depositing and etching a nitride liner to create a thin side wall nitride prior to the STI gap fill.
REFERENCES:
patent: 4352724 (1982-10-01), Sugishima et al.
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6339004 (2002-01-01), Kim
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6461937 (2002-10-01), Kim et al.
patent: 6465866 (2002-10-01), Park et al.
patent: 2002/0003275 (2002-01-01), Lee et al.
Stanley Wolf Silicon Processing for the VSLI Era vol. 2 Lattice Press 1990 pp. 52-53.
Chen Zhihao
Mansoori Majid M.
Mehrad Freidoon
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