Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2003-01-15
2004-10-05
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S107000, C438S119000, C204S164000
Reexamination Certificate
active
06800537
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor chip mounting and connection, and more particularly relates to methods of making anisotropic conductive elements for use in microelectronic packages.
Modern electronic devices utilize semiconductor components, commonly referred to as “integrated circuits,” which incorporate numerous electronic elements. These chips are typically mounted on substrates that physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be part of a discrete chip package, such as a single chip module or a multi-chip module, or may be a circuit board. The chip module or circuit board is typically incorporated into a large circuit. An interconnection between the chip and the chip module is commonly referred to as a “first level” assembly or chip interconnection. An interconnection between the chip module and a printed circuit board or card is commonly referred to as a “second level” interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip.
The rapid evolution of the semiconductor art in recent years has created an intense demand for semiconductor chip packages having progressively greater numbers of contacts in a given amount of space. An individual chip may require hundreds or even thousands of contacts, all within the area of the front face of the chip. Certain complex semiconductor chips currently being used have contacts spaced apart from one another at center-to-center distances of 0.1 mm or less and, in some cases, 0.05 mm or less.
One method utilized to interconnect semiconductor chips having closely spaced contacts includes using anisotropic conductive material. In U.S. Pat. No. 5,627,405, issued May 6, 1997, Chillara discloses an integrated circuit assembly comprising an integrated circuit, a dielectric substrate and an anisotropic electrically conductive layer interposed between the dielectric substrate and the integrated circuit. The anisotropic electrically conductive layer is electrically conductive in directions that are parallel to an electrically conductive axis and is electrically insulative in other directions.
However, there continues to be a need for improvement in elements and methods of making anisotropic conductive elements for use in microelectronic packaging.
SUMMARY OF THE INVENTION
In one preferred embodiment of the present invention, a method of making an anisotropic conductive element for use in microelectronic packaging includes the step of providing a layer of an anisotropic conductive material incorporating a dielectric material, such as a polymeric material or a curable silicone elastomer. The layer of anisotropic conductive material preferably includes a plurality of electrically conductive particles in the dielectric material. The dielectric material is preferably provided in a fluid or uncured condition. The dielectric material may be made more fluid by heating the anisotropic conductive material so that the viscosity of the material is reduced whereby the electrically conductive particles are relatively more free to move throughout the layer. The layer of anisotropic conductive material preferably has a pair of oppositely-directed major faces, a vertical direction between the major faces and horizontal directions parallel to the major faces.
The electrically conductive particles may include metal, such as solid metal balls, or elongated metal particles such as particles having longitudinal axes. The electrically conductive particles may also include elements having non-conductive cores which are coated with a layer of a conductive material. The non-conductive cores may include epoxy or other polymers, glass or silicone. Preferably, the conductive layers are provided uniformly about the cores.
A field is preferably applied to the layer of anisotropic conductive material so as to alter the configuration of the electrically conductive particles. The applied field may include an electrical field, a magnetic field or a combined electrical and magnetic field applied to the layer. In one preferred embodiment, the applying a field step includes biasing said first and second major faces with a different electrical potentials on at least some regions of the major faces. The electrically conductive particles preferably have longitudinal axes whereby the application of the electrical field turns the axes of elongation of at least some of the elongated particles toward the vertical direction. As a result, at least some of the electrically conductive particles are positioned in a substantially vertical direction between the major faces. Where the vertical dimension or thickness of the layer is larger than the longitudinal dimension of the particles, application of the field may bring some of the particles to a generally end-to-end disposition. The application of the field may also move at least some of the particles in horizontal directions so as to form areas of high particle concentration interspersed with areas of low particle concentration. The effects of turning the axes of elongation of at least some of the elongated conductive particles toward the vertical direction and moving at least some of the conductive particles in horizontal directions may be combined to provide areas of high particle concentration which generally include vertically-arrayed conductive particles which are closely congregated with one another. The areas of high particle concentration facilitate the conduction of electrical signals through the layer, from one major face of the layer to the second oppositely directed major face of the layer.
After the field has been applied to the layer of anisotropic conductive material so as to alter the configuration of the particles, the dielectric material is set or cured so that the dielectric material transforms into a non-fluid condition whereby the electrically conductive particles are substantially secured or frozen in place. In other words, the conductive particles are relatively less mobile throughout the dielectric material after the dielectric material has been set. However, in other embodiments the application of heat to set the curable dielectric material may occur simultaneously with the application of a field, such as a magnetic field.
The application of the magnetic or electrical field to the layer of anisotropic conductive material programs the layer preferably provides an interposer which may be juxtaposed between microelectronic elements for electrically interconnecting the microelectronic elements. The electrical and/or magnetic field generally alters the configuration of the particles to provide one or more substantially vertically-directed conductive paths through the layer of anisotropic conductive material. Each vertically-directed conductive path preferably includes a plurality of the electrically conductive particles which have been drawn into areas of high concentration by the application of the field. The programmed layer may be stored between one or more storage liners, such as thin flexible sheets of plastic. The storage liners protect the layer from contamination. A release treatment, such as TEFLON, may be disposed between the storage liners and the major surfaces of the layer of anisotropic conductive materials so that the storage liners may be easily removed from the layer prior to assembly with one or more microelectronic elements.
The layer prepared in accordance with the methods described above may also be used to electrically interconnect microelectronic elements. For example, a first microelectronic element such as a semiconductor chip having a plurality of contacts on a front surface thereof may be juxtaposed and abutted against the first major surface of the layer of anisotr
Ghyka Alexander
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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