Nonvolatile semiconductor memory device with double data...

Details Nonvolatile semiconductor memory device with double data... Nonvolatile semiconductor memory device with double data...

2003-03-04

2004-03-16

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185170

Reexamination Certificate

active

06707719

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a non-volatile semiconductor memory device and, more particularly, it relates to a memory device adapted to store multi-valued data and also to a method of storing such data of the device.
NAND type flush memory devices comprising an EEPROM that is an electrically writable non-volatile semiconductor memory have been proposed. In such a NAND type flush memory, the sources and the drains of a plurality of adjacently arranged memory cells are connected in series and the plurality of memory cells that are connected in series are connected to a bit line as a unit. Then, a set of data are collectively written in or read from all or half of the plurality of cells arranged in a row.
In recent years, multi-valued memories that can store a plurality of data (n-bit data) written into a single cell have been developed as NAND type flush memories. Such a multi-valued memory requires the use of n latch circuits for writing data to or reading data from a single cell in order to write a plurality of data to or reading a plurality of data from the single cell because the threshold value of the cell is determined by the contents of the data latched by the latch circuits.
However, as the number of data n that can be stored in a single cell increases, the number of latch circuits that is equal to n also increases to make them occupy the chip that contains them to a large extent.
Meanwhile, when storing data in a cell, an operation is conducted to verify that the threshold value of the cell properly corresponds to the written data. The number of verifying operations increases as the number of data to be written to a cell. Then, the time required for data writing and write-verifying operations increases for each cell.
BRIEF SUMMARY OF THE INVENTION
In view of the above identified problems, it is therefore the object of the present invention to provide a memory device that can effectively prevent the area occupied by the latch circuits in the chip from augmenting and also the time required for write-verifying operations from increasing and a storage method to be used by such a memory device.
According to the invention, the above object is achieved by providing a storage method of a memory device comprising memory cells (M
1
through M
16
) adapted to have 2
1
states for the first write operation, 2
2
states for the second write operation and 2
k
=n states (k, n representing respective natural numbers) for the n-th write operation, the method comprising: storing data of the first logic level or of the second logic level in data storage circuits in the k-th write operation; modifying the state “i−1” (i≦n−1, i being a natural number) of the memory cells to state “i” when the data of the data storage circuits are of the first logic level but maintaining the state of the memory cells when the data of the data storage circuits are of the second logic level; shifting the state of the data storage circuits from the first logic level to the second logic level when the state of the memory cells has already got to state “i” and currently is at any of “0” through “i”; holding the state of the data storage circuits to the first logic level when the state of the memory cells has not got to state “i” yet and currently is at any of “
0
” through “i”; holding the data of the data storage circuits when the state of the memory cells is at any of “i+1” through “n−1”; and controlling the state of the memory cells so as not to be modified from “i+1” to “n−1” even temporarily when the state of the memory cells is modified from “i−1” to “i”.
According to the invention, there is also provided a storage method of a memory device comprising memory cells adapted to have n-valued states, the method comprising: storing externally input data of the first logic level or of the second logic level in the data storage circuits of the device; shifting the logic level stored in the data storage circuits in response to the first logic level or the second logic level read out from the memory cells; and modifying the state of the memory cells when the shifted logic level stored in the data storage circuits is the first logic level but holding the state of the memory cells when the shifted logic level stored in the data storage circuits is the second logic level.
According to another aspect of the invention, there is provided a semiconductor memory device comprising: memory cells having n states including state “0”, state “1”, . . . and state “n−1” (2≦n, n being a natural number); a first data storage circuit for storing externally input data, the data being of the first logic level or of the second logic level; read circuits for reading the state of the memory cells; a second data storage circuit for storing data of the first logic level when the state of the memory cells read out by the read circuits is at any of “0” through “i” but storing data of the second logic level when the state of the memory cells read out by the read circuits is at any of “i” through “n−1”; write circuits for modifying the state of the memory cells from state “i−1” to state “i” when the data of the first data storage circuit are of the first logic level but holding the state of the memory cells when the data of the first data storage circuit are of the second logic level; a write verify circuit for shifting the data of the first data storage circuit from the first logic level to the second logic level when the state of the memory cells has already got to state “i” and the data of the second data storage circuit are of the first logic level but holding the data of the first data storage circuit when the state of the memory cells has not got to state “i” yet and the data of the second data storage circuit are of the first logic level and also when the data of the second data storage circuit are of the second level; and a write state control circuit for controlling the sate of the memory cells so as not to be modified from “i+1” to “n−1” even temporarily when the state of the memory cells is modified from “i−1” to “i”.
According to the invention, there is also provided a semiconductor memory device comprising: memory cells having n states including state “
0
”, state “1”, . . . and state “n−1” (2≦n, n being a natural number); a differential amplifier circuit having at least a differential amplifier for being supplied with the potential output from the memory cells at the first input terminal thereof and a reference potential different from the potential at the second input terminal thereof; a logic circuit for selectively taking out the output signal of the at least one differential amplifier; a data storage circuit connected to the memory cells for storing data of the first logic level or of the second logic level; and control circuits for modifying the state of the memory cells from “i−1” to “i” when the data of the data storage circuit are of the first logic level, maintaining the state of the memory cells when the data of the data storage circuit are of the second logic level, shifting the data of the data storage circuit from the first logic level to the second logic level when the state of the memory cells have already got to state “i” and currently is at any of “1” through “i”, holding the data of the data storage circuit to the first logic level when the state of the memory cells have not got to state “i” yet and currently is at any of “1” through “i”, holding the data of the data storage circuit when the state of the memory cells are at any of “i+1” through “n−1” and controlling the sate of the memory cells so as not to be modified from “i+1” to “n−1” even temporarily when the state of the memory cells is modified from “i−1” to “i”.
With a memory device and a storage method according to the invention, the area occupied by the latch circuits in the chip is prevented from augmenting and also the time required for write-verifying operations is suppressed and prevented from i

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