Surge limiting circuit with optional short circuit detection

Details Surge limiting circuit with optional short circuit detection Surge limiting circuit with optional short circuit detection

2003-05-20

2004-12-14

Vu, Bao Q. (Department: 2838)

Electricity: power supply or regulation systems

In shunt with source or load

Using choke and switch across source

C323S908000, C323S223000, C323S901000

Reexamination Certificate

active

06831447

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronic circuits for limiting inrush current and, more particularly, to a surge limiting circuit capable of limiting inrush current to a protected electronic circuit component, without reducing the steady-state effectiveness of the protected component within a circuit.
DESCRIPTION OF THE RELATED ART
The need to limit inrush current to prevent damage to electronic components, such as capacitors, is well established. One technique is to place a static impedance (e.g., a resistor) in series with the component to be protected to limit the amount of current that can pass through the component upon providing power to the circuit in which the component is used. The size of the resistor used is selected based upon the magnitude of the source and transient voltages expected to be applied to the circuit.
There are several problems associated with the use of static resistors in such a manner. Upon the circuit reaching a steady state condition, the static resistor impedance value remains in series with the protected component, resulting in undesirable effects. For example, the in-series impedance results in a wasteful dissipation of energy, long after the risk of damage due to inrush current has subsided. Furthermore, placing a resistor in series with a capacitor used to filter circuit transients reduces the effectiveness of the capacitor in filtering such transients due to the voltage across the in-series resistor. The magnitude of such undesirable effects, as well as the amount of surge protection provided by an in-series resistor, is directly proportional to the size of the in-series impedance. As a result, in choosing the size of an in-series static resistor, a circuit designer typically balances the amount of surge protection desired against the magnitude of the undesirable effects, described above.
It is well know in the art that many of the undesirable effects associated with using in-series static impedance to suppress inrush current can be avoided by replacing the in-series resistor with a Field Effect Transistor (FET) that provides dynamic in-series impedance. Typically the drain-to-source pathway of the FET is placed between the component to be protected, such as a capacitor, and ground and a small capacitor is connected between the FET gate terminal and the FET source terminal. The drain-to-source impedance of an FET is very high until a threshold voltage is applied to the FET gate to bias the FET in an “on” state, thus establishing a low impedance drain-to-source pathway. In conventional FET-based surge limiting circuits, when a power source is connected to the circuit, the capacitor between the FET gate and ground slowly builds charge creating an slow increase in the voltage across the capacitor (and hence the FET gate). In this manner, the FET slowly activates, and FET drain-to-source impedance is slowly diminished from a very high impedance value to a very low impedance value. Use of an FET in place of a static in-series resistor provides a high initial in-series impedance that gradually reduces to a nominal FET drain-to-source “on” impedance, typically on the order of 0.01 ohms. In this manner, many of the undesirable effects associated with a fixed in-series impedance are significantly reduced.
However, even after substitution of an FET to provide dynamic in-series impedance, several difficulties still remain. For example, conventional circuits do not adequately control the rate at which the FET gate capacitor charges under a wide variety of applied circuit voltages and transients. If the FET gate capacitor charges too rapidly, the in-series impedance provided by the FET may not be reduced slowly enough to avoid damage to the protected circuit element due to inrush current. Furthermore, methods used by conventional circuit designs to protect the FET from over-voltage gate conditions are not compatible with integrated circuit production techniques and often result in a significant shunt current during over-voltage conditions.
One conventional inrush protection approach based upon use of an FET is presented in U.S. Pat. No. 5,122,724, entitled, “Inrush Current Limiter” (hereinafter referred to as the '724 patent), suffers from both the undesirable effects described above.
FIG. 1
of the '724 patent is presented at
FIG. 1
herein and is labeled “Prior Art.” As described in the '724 patent, static impedance R
1
, shown in
FIG. 1
, is used to control the voltage applied to the FET gate, and thus, the value of the in-series drain-to-source impedance of FET Q
1
under steady-state conditions.
While such an approach may be sufficient under controlled voltage conditions, the current through R
1
is based upon the voltage across load resistor R, which is subjected to transients. Thus, the rate at which current flows into gate capacitor C
1
can vary, resulting in gate capacitor C
1
charging at an unpredictable rate and reaching the gate threshold voltage in an unpredictable amount of time. Such a condition can result in reduction of the in-series FET drain-to-source impedance at too rapid a rate, resulting in significant inrush current into, and potential damage to, capacitor C
2
.
Another deficiency associated with the circuit described in patent '724 is the use of a zener diode to protect the FET from gate over-voltage conditions. Such a zener diode is needed because R
1
, cannot protect the FET gate from over-voltage conditions resulting from uncontrolled voltage conditions across load resistor R, as described above. Such zener diodes are difficult to construct using integrated circuit production techniques, resulting in increased production costs or forcing the use of a discrete zener diode component, thereby increasing circuit board real-estate and increasing the number of soldered circuit connections, and hence, increasing production defect rates and increasing field failure rates of the surge limiting circuit.
Hence, a surge limiting circuit is needed that maintains positive control over the flow of current that charges the FET gate capacitor, thereby maintaining positive control over the rate at which the FET turns-on, the rate at which FET drain-to-source impedance is diminished, and the rate of inrush current into a protected circuit component. Further, a surge limiting circuit is needed that eliminates the need for zener diode over-voltage protection of the FET gate, thereby reducing production costs, decreasing circuit defect rates and increasing surge limiting circuit reliability.
SUMMARY OF THE INVENTION
Therefore, in light of the above, and for other reasons that will become apparent when the invention is fully described, an object of the present invention is to protect sensitive circuit components against inrush current over a wide variety of input power conditions, without affecting steady-state performance of the protected circuit components.
A further object of the present invention is to maintain positive control over the duration and level of inrush protection provided to a protected circuit component despite a wide variety of input power conditions.
Yet a further object of the present invention is to improve performance and reduce the cost of producing circuits that include inrush current protection.
A still further object of the present invention is to improve performance and reduce the cost of producing discrete electronic components with integrated inrush circuit protection.
The aforesaid objects are achieved individually and in combination, and it is not intended that the present invention be construed as requiring two or more of the objects to be combined unless expressly required by the claims attached hereto.
In accordance with the present invention, a surge limiting circuit is described for limiting an inrush current through a protected circuit path in a circuit in response to application of power to the circuit. A non-limiting, representative embodiment of the present invention includes a field effect transistor connected in series with the protected circuit path and

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