Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth with a subsequent step acting on the...
Reexamination Certificate
2002-11-19
2004-08-10
Hiteshew, Felisa (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth with a subsequent step acting on the...
C117S003000, C117S009000, C438S597000
Reexamination Certificate
active
06773502
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to formation of crystalline phase materials in semiconductor wafer processing and more particularly to formation of refractory metal suicides and crystalline phase transformation thereof.
BACKGROUND OF THE INVENTION
Silicides, such as titanium silicide and tungsten silicide, are commonly utilized electrically conductive materials in semiconductor wafer integrated circuitry fabrication. Such materials are utilized, for example, as capping layers over underlying conductively doped polysilicon material to form electrically conductive lines or interconnects. Such silicide materials are also utilized at contact bases intermediate an underlying silicon substrate and overlying conductive polysilicon contact plugging material. Silicides can be provided by chemical vapor deposition, or by deposition of elemental titanium or tungsten over an underlying silicon surface. Subsequent high temperature annealing causes a chemical reaction of the tungsten or titanium with the underlying silicon to form the silicide compound.
Titanium silicide (TiSi
2
) occurs in two different crystalline structures or phases referred to as the C49 and C54 phase. The C49 structure is base-centered orthorhombic, while the C54 is face-centered orthorhombic. The C54 phase occurs in the binary-phase diagram while the C49 phase does not. The C49 phase is therefor considered to be metastable. The C54 phase is a densely packed structure having 7% less volume than the C49 phase. The C54 phase also has lower resistivity (higher conductivity) than the C49 phase.
The C49 phase forms at lower temperatures during a typical refractory metal silicide formation anneal (i.e. at from 500° C.-600° C.) and transforms to the C54 phase at higher elevated temperatures (i.e., greater than or equal to about 650° C.). The formation of the higher resistive C49 phase has been observed to be almost inevitable due to the lower activation energies associated with it (2.1-2.4 eV) which arises from the lower surface energy of the C49 phase compared to that of the more thermodynamically stable C54 phase. Hence, the desired C54 phase can be obtained by transforming the C49 phase at elevated temperatures.
Due at least in part to its greater conductivity, the C54 phase is much more desirable as contact or conductive line cladding material. Continued semiconductive wafer fabrication has achieved denser and smaller circuitry making silicide layers thinner and narrower in each subsequent processing generation. As the silicide layers become thinner and narrower, the ratio of surface area to volume of material to be transformed from the C49 to the C54 phase increases. This requires ever increasing activation energies to cause the desired transformation, which translates to higher anneal temperatures to effect the desired phase transformation. In some instances, the temperature must be at least equal to or greater than 800° C. Unfortunately, heating a silicide layer to a higher temperature can result in undesired precipitation and agglomeration of silicon in such layer, and also adversely exposes the wafer being processed to undesired and ever increasing thermal exposure. The processing window for achieving or obtaining low resistance silicide phases for smaller line widths and contacts continues to be reduced, making fabrication difficult.
It would be desirable to develop methods which facilitate the C49 to C54 phase transformation in titanium silicide films. Although the invention was developed with an eye towards overcoming this specific problem, the artisan will appreciate applicability of the invention in other areas, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.
SUMMARY
In but one aspect, the invention provides a method of forming a crystalline phase material. In one implementation, the method is performed by providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase prior to anneal. The crystalline material of the first crystalline phase is annealed under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase.
In accordance another aspect, the invention provides a method of forming a refractory metal silicide. In one implementation, the method is performed by forming a refractory metal silicide of a first crystalline phase. Compressive stress inducing atoms are provided within the refractory metal silicide of the first crystalline phase, with the compressive stress inducing atoms being larger than silicon atoms of the silicide. With the compressive stress inducing atoms within the first phase refractory metal silicide, the refractory metal silicide of the first crystalline phase is annealed under conditions effective to transform said silicide to a more dense second crystalline phase.
In another implementation, a stress inducing material is formed over the opposite side of the wafer over which the first phase crystalline material is formed.
REFERENCES:
patent: 4337476 (1982-06-01), Fraser et al.
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 4568565 (1986-02-01), Gupta et al.
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 4971655 (1990-11-01), Stefano et al.
patent: 5240739 (1993-08-01), Doan et al.
patent: 5376405 (1994-12-01), Doan et al.
patent: 5593924 (1997-01-01), Apte et al.
patent: 5608266 (1997-03-01), Agnello et al.
patent: 5665646 (1997-09-01), Kitano
patent: 5828131 (1998-10-01), Cabral, Jr. et al.
patent: 5874351 (1999-02-01), Hu et al.
patent: 6054387 (2000-04-01), Fukuda
patent: 6090708 (2000-07-01), Sandhu et al.
patent: 6306766 (2001-10-01), Sandhu et al.
patent: 6376372 (2002-04-01), Paranjpe et al.
patent: 8139056 (1996-05-01), None
Ma et al., “Manipulation of the Ti/Si reaction path by introducing an amorphous Ge interlayer”, 4thinternational conference on Solid-state and Integrated circuit technology Proceedings, 1995, pp. 35-37.
Ilderem, V., et al., “Optimized Deposition Parameters For Low Pressure Chemical Vapor Deposited Titanium Silicide”,Massachusetts Institute of Technology, vol. 135, No. 10, pp. 2590-2596 (Feb. 1988).
Nagabushnam, R.V., et al., “Kinetics And Mechanism Of The C49 to C54 Titanium Disilicide Phase Transformation Formation in Nitrogen Ambient”. 3 pages (Nov. 1995).
Huang, et al. The Influence of Ge-Implantation on the Electrical Characteristics of the Ultra-Shallow . . . IEEE Electron Device Letters, vol. 17. No. 3. Mar. 1996, pp. 88-90.
M. Ali Omar, “Elementary Solid State Physics” © 1975 by Addison-Wesley Publishing Company, Inc., pp. 539-542.
Wolf, et al., “Silicon Processing for the VLSI Era—vol. 1-Process Technology”, ©1986 by Lattice Press pp. 242, 261, 262, 303 and 304.
Sandhu Gurtej S.
Sharan Sujit
LandOfFree
Method of forming a crystalline phase material does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a crystalline phase material, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a crystalline phase material will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3279739