Clock generator, clock generating method, and signal receiver

Details Clock generator, clock generating method, and signal receiver Clock generator, clock generating method, and signal receiver

2000-06-28

2004-03-16

Vo, Don N. (Department: 2631)

Pulse or digital communications

Synchronizers

C375S376000

Reexamination Certificate

active

06707866

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an interface for use in DVB (Digital Video Broadcast)-T, and more particularly to an apparatus for generating a clock signal, a method of generating a clock signal, and a signal-receiving method.
BACKGROUND ART
FIG. 1
is a block diagram showing a conventional receiving system
10
that utilizes orthogonal frequency division multiplex (OFDM).
This receiving system
10
comprises an OFDM receiver
2
connected to an antenna
1
, an MPEG2 decoder
3
connected to the OFDM receiver
2
, and a monitor apparatus
4
connected to the MPEG2 decoder
3
.
In the receiving system
10
, the OFDM receiver
2
receives the electric waves that the antenna
1
has caught.
The OFDM receiver
2
is composed of an OFDM receiving section
5
, a rate converting section
6
, and a clock generating section
7
. The OFDM receiving section
5
receives a signal supplied from the antenna
1
and demodulates the signal. The clock generating section
7
generates a clock signal from the signal input from the OFDM receiving section
5
. The rate converting section
6
converts the rate of the signal input from the OFDM receiving section
5
and outputs the rate to the MPEG2 decoder
3
.
The MPEG2 decoder
3
decodes the input signal in accordance with the MPEG2 standards and outputs a reproduced image signal to the monitor apparatus
4
. The monitor apparatus
4
displays the image represented by the input image signal.
The OFDM receiving section
5
and the rate converting section
6
, both incorporated in the OFDM receiver
2
, may be replaced in practice by a device that performs the functions of them. In this case, too, the clock generating section
7
needs to use the clock signal regenerated from the received signal and to generate a new clock signal suitable for the transmission mode.
This will be described in detail as follows.
In the TS interface for DVB (Digital Video Broadcast)-T, there are used TPS (Transmission Parameter Signaling) carriers as signaling parameters concerning the transmission processes such as channel coding and modulation. A guard interval length GIL, a modulation/demodulation mode, a coding ratio (bank chad number) and the like are given as the signaling parameters. The TS interface for DVB-T is based on the super-frame concept. The transmission mode can therefore be changed for each super frame in the TS interface. (In practice, the mode is seldom changed.) If the transmission mode is changed, the rate of TSI clock will change.
There are various kinds of transmission modes concerning the clock rate. They are a coding ratio, a modulation system and a guard interval. The number of clocks in one super frame and the number of MPEG2 packets (each consisting of 188 data items) for the super frame depend upon these three parameters. It is therefore necessary to generate a clock signal for each parameter within the super frame, in order to make an access, at a constant clock rate, to the MPEG2 encoder of the transmitting side. There are 60 possible combinations of these parameters. Their frequency-dividing ratios are complex. The clock signal on the transmitting side has the frequency of 9.143[MHz] (=64/7[MHz]), and the access request to the MPEG2 encoder has the frequency ranging from 0.677[MHz] to 4.295[MHz].
The OFDM receiving section
5
of the OFDM receiver
2
includes an OFDM demodulation block, a Viterbi decoding block, and an RS (Read-Solomon) decoding block. The OFDM demodulation block has parameters for the guard interval length and the modulation/demodulation mode. The Viterbi block has a parameter for the coding ratio (bank chad number). In the guard interval of the OFDM demodulation block, for example, there exists ineffective data that amounts to a quarter (¼) of the effective data. If a method in which the ineffective data is transmitted to the next block, together with the control signal identifying the ineffective data, is employed, the data rate valid at present will not change and the rate will not be converted, either. On the other hand, if a method in which a clock signal having a cycle that is {fraction (5/4)} of the present data rate is used and only the effective data is transmitted to the next block, it will be necessary to convert the rate when the data is output from the OFDM demodulation block. In this case, the OFDM receiving section
5
and the rate converting section
6
must be replaced by a device that performs their functions.
No matter whether the data rate is converted for each block or for all blocks at a time, there is required a clock signal that has a rate different from that of the clock signal regenerated in the OFDM demodulation block. For example, the above-mentioned clock signal having a {fraction (5/4)} cycle needs to be used. The guard interval length may be ¼ or ⅛. It follows that a clock signal having a {fraction (5/4)} cycle or a clock signal having a {fraction (9/8)} cycle is required. That is, a desired clock signal must be generated for each transmission mode (parameter).
PLL (Phase Locked Loop) technique has hitherto been used to generate and regenerate clock signals.
FIG. 2
is a block diagram illustrating the basic structure of the clock generating section
7
that utilizes the conventional PLL technique. The signal output from a reference signal oscillator
11
(i.e., a signal corresponding to the signal that the OFDM receiving section
5
has generated from the signal it had received) is input to a phase comparator
12
. The phase comparator
12
generates a phase-difference signal from the input signal and the output of a voltage-controlled oscillator
14
. The phase-difference signal is output to an LPF (Low-Pass Filter)
13
. The LPF
13
removes the unnecessary high-frequency component from the input signal, generating a signal. The output signal of the LPF
13
is supplied to the voltage-controlled oscillator
14
. The voltage-controlled oscillator
14
generates a clock signal that has a frequency corresponding to the level of the input signal. The clock signal is output from a clock output terminal
15
and supplied to the phase comparator
12
. The characteristics of the LPF
13
greatly influence the operating characteristics of the PLL. In view of this, the characteristic design of the LPF
12
is of vital importance.
FIG. 3
is a block diagram depicting another structure the clock generating section
7
may have. The clock generating section
7
shown in
FIG. 3
has a first frequency divider
21
and a second frequency divider
22
in addition to the components of the basic structure illustrated in FIG.
2
. The first frequency divider
21
frequency-divides the signal output from the reference signal oscillator
11
, generating a signal. The signal is supplied to the phase comparator
12
. The second frequency divider
22
frequency-divides the signal output from the voltage-controlled oscillator
14
, thus generating a signal. This signal is supplied to the phase comparator
12
.
The first frequency divider
21
divides the frequency of the signal output from the reference signal oscillator
11
by m. The second frequency divider
22
divides the frequency of the signal output from the reference signal oscillator
11
by n. The phase comparator
12
compares the signals input from the first frequency divider
21
and second frequency divider
22
, in terms of phase, and generates a phase-difference signal. The LPF
13
removes the unnecessary high-frequency component from the phase-difference signal and outputs the phase-difference signal to the voltage-controlled oscillator
14
. The voltage-controlled oscillator
14
generates a clock signal that has the frequency corresponding to the input signal. The clock signal is output from the clock output terminal
15
.
The characteristics of the LPF
13
greatly influence the operating characteristics of the clock generating section, such as that required to obtain a desired output clock signal, the operating stability after the generation of the c

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