Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-01-16
2004-11-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C438S296000, C438S694000, C438S710000, C438S712000, C438S720000
Reexamination Certificate
active
06818995
ABSTRACT:
TECHNICAL FIELD
The present invention relates to multiple layered structures of semiconductor devices, and more particularly to semiconductor devices using damascene structures, which can accommodate higher integration, further miniaturization, lower resistances and higher operation speeds, and methods for manufacturing the same.
BACKGROUND
For semiconductor integrated circuit devices, there is a tendency to use low resistance Cu wiring material that can accommodate higher circuit integrations, lower voltage power supplies and higher operation speeds pursued in recent years. The use of a damascene method that includes embedding wiring material and chemical mechanical polishing (CMP) has become the main stream in processes with Cu wiring material.
For example, a lithography technique is used to selectively form an opening in an interlayer dielectric film to expose contact region. A trench that is to become a wiring region may be formed with the contact region. Then, the contact region is coated with barrier metal material such as Ti/TiN stacked layers, TaN, WN or the like by a sputter method.
Next, a Cu wiring material is embedded. For this purpose, a sputtering of a Cu seed layer or a deposition of Cu by an electrolytic plating method is generally practiced. By performing such a method, a Cu wiring material is deposited on the contact region and a region including a trench (wring trench) that is to become a wiring region. Then, a chemical mechanical polishing (CMP) technique is conducted to form a structure in which the Cu wiring material is embedded in only necessary wiring sections.
FIG. 11
shows a cross-sectional view of a conventional multiple wiring layer structure with Cu wiring material. A Cu wiring member
41
in a lower layer connects through a contact region to a Cu wiring member
42
in an upper layer. Each of the Cu wiring members is coated on its circumference with a barrier metal BM having an appropriate thickness as a base layer. By this, diffusion of Cu into an interlayer dielectric film
40
(
402
) and the contact region is prevented.
Also, for forming a wiring trench
421
, a stopper film ES, which can define an etching selection ratio with respect to the interlayer dielectric film
40
, is formed. This plays a role in accurately forming a bottom section of the wiring trench
421
. For example, when the interlayer dielectric film
40
is a silicon oxide film, the stopper film ES may be composed of, for example, a silicon nitride film.
Further, before forming a via hole
422
that is to become a contact region with respect to an upper layer, a diffused barrier layer
413
is also provided on the Cu wiring member
41
. The diffused barrier layer
413
may be, for example, a silicon nitride film in the above example. By this, diffusion of Cu into an interlayer dielectric film
402
(silicon nitride film) to be deposited next or the like is prevented.
In the structure described above, the barrier metal BM having an appropriate thickness is coated as a base for the Cu wiring member to prevent Cu from diffusing into the contact region. Since the barrier metal material has a higher resistance than the Cu wiring material, the barrier metal material is currently formed as thin as possible.
FIG. 12
shows a cross-sectional view illustrating problems with the structure shown in FIG.
11
. The same reference numbers are assigned for the same sections shown in FIG.
11
. Due to advanced miniaturization, a contact region CTA is reduced. There is a high risk that etching positions at the contact region CTA may partially deviate from one another due to a slight matching deviation in the photolithography process. As for the example shown in the figure, voids may be generated due to excessive etching, Cu may diffuse due to a lack of the barrier metal, there is a possibility of increased defects, and there is a possibility of a short-circuit among adjacent wirings.
The present invention has been made in view of the problems discussed above, and one object is to provide a semiconductor device having a highly reliable connecting wiring structure with minute multiple wiring layers composed of embedded Cu wiring material which form an integrated circuit, and a method of manufacturing the same.
SUMMARY
A semiconductor device in accordance with the present invention pertains to a semiconductor device formed from multiple wiring layers having predetermined metal wiring members arranged therein, and is characterized in comprising: a dielectric film between layers of the multiple wiring layers, the dielectric layer having a first dielectric film composing a major part thereof and having a first etching selection ratio, and a second dielectric film at least adjacent to the first dielectric film, composing an edge section side wall of a connecting region of the metal wiring layers and having a second etching selection ratio.
By the semiconductor device of the present invention described above, a second dielectric film, which has an etching selection ratio different from that of the first dielectric film, is disposed at the edge section side wall of a connecting region of the metal wiring layers. As a result, when forming metal wiring members, and when a wiring layer in an upper layer is connected to a wiring layer in a lower layer through a via hole formed in the first dielectric film by etching, an etching deviation at an edge section of the lower wiring layer can be compensated by the amount of the thickness of the second dielectric film.
In view of the relations between the first dielectric film and the second dielectric film, a variety of combinations of these films can be possible. First, it is characterized in that the second dielectric film may be selected from nitride films or oxide films. Also, a variety applications are possible in selecting the first dielectric film. For example, any one of an inorganic film, an organic film with a low dielectric constant, an inorganic film with a low dielectric constant and a porous film with a low dielectric constant having pores introduced in the film may be used.
Further, it is characterized in that a barrier metal is present in a predetermined region between the second dielectric film and the metal wiring member, which is effective when the second dielectric film having a poor capability to prevent diffusion of the metal wiring member is selected. Even when the second dielectric film has a poor capability to prevent diffusion of the metal wiring member, an addition of the barrier metal improves the capability of preventing diffusion of the metal wiring member into the first dielectric film.
More preferably, it is characterized in that the barrier metal is provided between the second dielectric film except a via-contact side wall at the connecting region of the metal wiring members and the metal wiring member. When the selected second dielectric film has a capability to prevent diffusion of the metal wiring member, the addition of the barrier metal may result in a higher resistance with respect to the via contact that has a narrow connecting area. Therefore, it is sufficient to provide the via-contact side wall only with the second dielectric film having a capability of preventing diffusion of the metal wiring member.
A method of manufacturing in accordance with the present invention pertains to a method of manufacturing a semiconductor device formed with circuit wirings including predetermined metal wiring members, and the method is characterized in comprising the steps of: forming a wiring region including an excess portion that is larger than a substantive wiring region by a predetermined measurement by selectively removing at least a first dielectric film having a first etching selection ratio; forming a second dielectric film having a second etching selection ratio such that at least the excess portion on a surface in the wiring region is embedded; conducting an anisotropic etching to leave the second dielectric film on a side wall including the excess portion of the wiring region; and embedding the wiring region with a metal wiring
Harness & Dickey & Pierce P.L.C.
Seiko Epson Corporation
Tran Mai-Huong
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