Electrical computers: arithmetic processing and calculating – Electrical hybrid calculating computer – Particular function performed
Reexamination Certificate
2001-01-02
2004-03-09
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical hybrid calculating computer
Particular function performed
C708S801000
Reexamination Certificate
active
06704757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor arithmetic unit and, more particularly, to an integrated circuit system which can perform an arithmetical operation such as image processing using multivalue or analog signals at high speed and with a high degree of accuracy.
2. Description of the Related Arts
A technique of real-time data compression according to transmission capacities of communication lines has been required in order to transmit motion picture data including much amount of information to remote places. As one means of this data compression, there is a technique of vector quantization. After comparing an arbitrary vector having a dimensional number with a plurality of different vectors having the same dimensional number (code book) previously prepared to select the most similar vector from all the vectors, the vector quantization quantizes an original vector on the basis of the pattern number of the selected vector. If the number of vectors in the code book (code vectors) is smaller than any number which the original vector may acquire, data is compressed. Decompression only needs to take out the vector corresponding to the number from the code book. Accordingly, it is widely known that the vector quantization is a data compression algorithm in which decompression can be performed very simply.
Some dedicated digital processors have been developed in order to perform this vector quantization operation in parallel and at high speed. In these dedicated processors, a correlator is generally disposed in parallel which compares a vector to be quantized with a code vector to execute quantification of the both similarities, and the similarities for all of the code vectors are simultaneously calculated in parallel. A distance between vectors is generally used with respect to this similarity, and the smallest distance is assumed to be the largest similarity.
Accordingly, the speed of the vector quantization can be made faster by providing a circuit which simultaneously receives the distance data in parallel from the correlator and retrieves the smallest value in the block. However, all of processing circuits were constituted of digital circuits, so that, as a result, the scale of the hardware essentially became very large. In particular, as the correlator realized by digital circuits required a lot of adders, there was a problem that the correlator occupied the largest scale.
One technique to solve this problem is to introduce analog or multivalue operation with a very simple circuitry into the processing circuits. From such a point of view, a report with respect to a binary-multivalue-analog merged operation processing circuit has been performed which uses a neuron-MOS transistor, a first-time four terminal device. Using this circuit enables the correlator to be constituted of very simple circuits. Distance data with analog and multivalue formats are outputted from such a correlator. There has been used a Winner-Take-All circuit employing a neuron-MOS comparator which can be set threshold values according to the distance data, as an operation circuit to determine a minimum value in these distance data. This enables the operation to find the minimum value in the distance data to be replaced with that of finding a maximum or minimum value of threshold values of the neuron-MOS comparator. The operation of finding a maximum or minimum value of threshold values of the neuron-MOS comparator can be achieved by inputting a common reference voltage to all comparators and by controlling the comparators to invert only the outputs of the comparators having a maximum or minimum threshold value. For this purpose, a ramp scan method has been proposed and the operation thereof has been confirmed (Refer to, for example, Japanese Patent Publication No. Hei 6-244375). This method operates such that the reference voltage is flatly changed over the entire dynamic range, and at the instant a neuron-MOS comparator with the maximum or minimum threshold value inverted, a latch signal is outputted in order to latch the output value of the comparator to a register at that moment. This method is very simple and easy to understand. However, in principle, there is a trade-off relation between the sweep rate of the reference voltage and the retrieval accuracy, and when trying to execute a high speed retrieval, deterioration of the retrieval accuracy is essentially unavoidable. That is, when a high speed sweep is execute, while a maximum value is detected and the latch signal is transmitted to the register, the reference voltage is further changed by a ramp scan, causing a neuron-MOS comparator with another threshold value included in the voltage range corresponding to its change to be inverted. In particular, when the ramp scan method is employed, the retrieval is performed with a monotonic sweep of one reference voltage, so that when attempting to make sure of the retrieval accuracy, a very slow sweep is required in practice over the entire dynamic range, forcing essentially the search time to be prolonged. One method for improving this problem is to make a transmittance delay time of the latch signal short by improving a circuit configuration. However, there is also a limitation in this method.
Furthermore, in a circuit employing a conventional ramp scan method, there was a problem in that a ramp scan signal should be externally inputted. For this problem, a technique of the prior art (Japanese Patent Publication No. WO 96/30855), as shown in
FIG. 18
, is provided. That is, a semiconductor operation circuit having one or more neuron-MOS transistors with plural input gate electrodes is characterized by having an inverter circuit group including a plurality of inverter circuits composed of the neuron-MOS transistor, having a means which applies a predetermined signal voltage to a first input gate of at least one of the inverter circuits, inputting output signals to a logical operation circuit, the output signals being obtained by causing output signals of all of the inverters included in the inverter circuit group to pass through a predetermined number of stages of inverter circuits, and feeding back an output signal of the logical operation circuit or the output signal obtained by causing the output signal of the logical operation circuit to pass through a predetermined number of stages of the inverter circuits to a second input gate of at least one of the inverter circuits included in the inverter circuit group. This allows a reference voltage to be produced inside of the semiconductor operation circuit. However, as the circuit is formed by a feedback configuration, the reference voltage constantly oscillates with a certain amplitude, therefore, a problem has developed concerning high accuracy analog voltage comparison operation.
Accordingly, the present invention is performed to solve those above described problems, and it is an object of the present invention to provide a semiconductor arithmetic unit realizing a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor composed of a binary-multivalue-analog merged operation processing circuit. Further, it is another object of the present invention to add a function for retrieving a vector with a distance of necessary order to the unit.
SUMMARY OF THE INVENTION
The present invention is characterized in that, in a multi-loop circuit comprising an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which at least one first electrode and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group, the second amplifyi
Morimoto Tatsuro
Nakada Akira
Nitta Takahisa
Ohmi Tadahiro
Shibata Tadashi
Knuth Randall J.
Mai Tan V.
Ohmi Tadahiro
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