Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2002-07-02
2004-11-02
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S750000, C438S754000, C134S001100, C134S001200
Reexamination Certificate
active
06812156
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor wafer manufacturing and more particularly to methods for depositing PVD and CVD layers to reduce particulate contamination.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
For example, in creating a multiple layer semiconductor device on a semiconductor wafer, each layer making up the device may be subjected to one or more deposition processes, for example using chemical vapor deposition (CVD) or physical vapor deposition (PVD), and usually including one or more etching procedures by either a dry (plasma) or wet (chemical) etching process. A critical condition in semiconductor manufacturing is the absence of contaminants on the wafer processing surface, since contaminants including, for example, microscopic particles, may interfere with and adversely affect subsequent processing steps leading to device degradation and ultimately semiconductor wafer rejection.
While the wafer cleaning process has always been a critical step in the semiconductor wafer manufacturing process, ultra clean wafers are becoming even more critical to device integrity. For example, as semiconductor feature sizes decrease, the detrimental effect of particle contamination increases, requiring removal of ever smaller particles. For example, particles as small as 5 nm may be unacceptable in many semiconductor manufacturing processes. Further, as the number of device layers increases, for example to 5 to 8 layers, there is a corresponding increase in the number of cleaning steps and the potential for device degradation caused by contamination. To adequately meet requirements for ultra clean wafers in ULSI and VLSI the wafer surface must be free of contaminating particles.
Another factor in modern processing technology that increases the incidence of particle contamination is the deposition of carbon doped oxides as IMD layers to achieve dielectric constants of less than about 3.0. The IMD layers are typically deposited by a plasma enhanced CVD (PECVD), low pressure CVD (LPCVD) or high density plasma CVD (HDP-CVD). In theses processes, a degree of sputtering occurs as the layer of material is deposited causing a higher degree of particulate contamination as the deposition time increases. In addition PVD processes are typically used to deposit films of metal, for example barrier/adhesion layers within anisotropically etched features or for metal filling an anisotropically etched feature. PVD processes tend to coat the inner surfaces of the processing chamber with a metal film, flaking off to contaminate a wafer process surface as the metal film increases in thickness and are subjected to cyclic thermal stresses. Again, the degree of particulate contamination depositing on the process surface increases with the thickness of the film being deposited.
Common processes in use for cleaning wafers include cleaning solutions based on hydrogen peroxide. At high pH values (basic) organic contamination and oxidizable particles, are removed by an oxidation process. At low pH (acidic) metal contamination is desorbed from the water surface by forming a soluble complex.
Typically, to reduce processing times and increase throughput, in prior at processes, an ex-situ cleaning process is performed following film deposition. For example, common particle removal mechanisms which may be exploited, depending on the particle and how it adheres to the surface, include dissolution, oxidizing degradation and dissolution, physical removal by etching, and electrical repulsion between a particle and the wafer surface.
Standard wafer cleaning processes include mechanical scrubbing and ultrasonic agitation of the wafer surface in a cleaning solution or in deionized water to effectuate particulate removal.
One shortcoming with the prior art method for depositing CVD and PVD layers making up a semiconductor device is that particulates may accumulate within the deposited layer producing defects including voids and particle inclusions that are difficult to detect following deposition. For example, automated optical scanning methods are typically used to detect and count particulate contamination at the wafer process surface following film deposition. Unfortunately, the effect of included particles may not be detected until several manufacturing processes have been performed and the process wafer fails wafer acceptance testing (WAT). The effect of the particulate inclusions may not manifest itself for a period of time, but increases reliability concerns of the semiconductor device. For example, the included particles may form localized areas of high stress increasing the probability of crack initiation during subsequent stress inducing manufacturing processes or environmentally induced stresses including, for example thermal cycling stresses. As a result, device yield and reliability is adversely affected.
There is therefore a need in the semiconductor processing art to develop a method whereby the incidence of particulate contamination during PVD or CVD processes is reduced.
It is therefore an object of the invention to develop a method whereby the incidence of particulate contamination during PVD or CVD processes is reduced, while overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method of reducing particulate contamination in a deposition process.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface for depositing a deposition layer thereover according to one of a physical vapor deposition (PVD) and a chemical vapor deposition (CVD) process; depositing at least a portion of the deposition layer over the process surface; cleaning the semiconductor wafer including the process surface according to an ex-situ cleaning process to remove particulate contamination including at least one of spraying and scrubbing; and, repeating the steps of depositing and cleaning at least once to include reducing a level of occluded particulates.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
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patent: 6432836 (2002-08-01), Watanabe
patent: 6598610 (2003-07-01), Blain et al.
patent: 6645550 (2003-11-01), Cheung et al.
Chu Hsing-Yuan
Day Dyson
Li Mei-Yen
More Ming-Te
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
Vinh Lan
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