Pulse or digital communications – Synchronizers
Reexamination Certificate
2000-02-18
2004-04-13
Ghebretinsae, Temesghan (Department: 2631)
Pulse or digital communications
Synchronizers
C375S374000, C327S151000
Reexamination Certificate
active
06721377
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the field of electronics. The invention relates to a method for resynchronizing a clock signal and to a circuit configuration for resynchronizing a clock signal.
When producing a clock signal from a reference clock signal, it is frequently necessary to resynchronize the clock signal in order to keep deviations from the reference clock signal as small as possible. To ensure small deviations, resynchronization circuits—also called phase locked loops (PLL)—are used. A resynchronization circuit is a control circuit in which the reference clock signal and the clock signal are continually compared and, based upon the comparison, the clock signal is resynchronized using a control circuit. Essential information on resynchronization circuits (PLLs) can be found, for example, in Tietze, Schenk “Electronic Circuits Design and Applications”, 1990, a translation of Tietze, Schenk “Halbleiter Schaltungstechnik [Semiconductor Circuitry]”, Ninth Edition, 1990. PLLs are usually constructed as analog circuits. However, there is a disadvantage related to changing the clock signal in analog circuits. To make such a change, either the PLL circuitry needs to be changed or the PLL needs to have adjustable parameters, both of which are very complicated to produce when using analog circuitry. Furthermore, the circuit complexity is greatly increased when producing very accurate analog circuitry PLLs.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method and a circuit configuration for resynchronizing a clock signal that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that has a high degree of accuracy and can easily be matched to different requirements.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for resynchronizing a clock signal, including the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce the frequency of a second clock signal, measuring the second clock signal with a digital control circuit, and programming a programmable digital frequency divider with the digital control circuit such that the second clock signal corresponds to the presettable clock signal.
For resynchronization, the method according to the invention uses only digital means, which are easy to produce and can be matched to different requirements by simple reprogramming.
In accordance with another mode of the invention, a third signal is defined and the measuring step is performed by measuring the second clock signal with the digital control circuit at time intervals predetermined by the third signal.
The digital control circuit preferably measures the second clock signal at time intervals predetermined by a third signal. Resynchronization is then advantageously carried out only at instants predetermined by the third signal. Thus, by adjusting the third signal, it is possible to set the time intervals for the measurements by the digital control circuit, and, therefore, the resynchronization instants. This is particularly advantageous if resynchronization is required only at particular instants.
In accordance with a further mode of the invention, a program is processed with the digital control circuit for establishing a discrepancy between the second clock signal and the presettable clock signal.
A particular preference is that the digital control circuit processes a program that establishes a discrepancy between the second clock signal and the presettable clock signal. By changing the program for establishing the discrepancy between the second clock signal and the presettable clock signal, it is possible to respond to a wide variety of requirements.
The advantage of the method according to the invention is, thus, the adaptability to different requirements and the simple manufacture that results by using digital means.
With the objects of the invention in view, there is also provided a circuit configuration for resynchronizing a clock signal, including a programmable digital frequency divider for dividing a first clock signal to produce second clock signal, a digital measuring circuit, connected to the frequency divider, for measuring the second clock signal and generating an output signal, and a digital control circuit, connected to the frequency divider and to the measuring circuit, for evaluating the output signal from the measuring circuit and, based upon the evaluation, for adjusting the frequency divider.
In accordance with an added feature of the invention, the second clock signal has pulses and the measuring circuit has a counter that counts the pulses of the second clock signal and a first register that stores a counter value of the counter.
In accordance with an additional feature of the invention, the control circuit has a microcontroller and a program memory.
A particular preference is that the digital control circuit has a microcontroller and a program memory. The microcontroller processes a program that is stored in the program memory and resynchronizes the second clock signal with the presettable clock signal. Simple reprogramming of the program memory allows the resynchronization algorithm to be matched to different requirements.
In accordance with a concomitant feature of the invention, there is provided a second register, the frequency divider to be digitally adjusted with the second register, the second register to be written to by the control circuit.
The programmable digital frequency divider can preferably be adjusted digitally by the second register, which can be written to by the digital control circuit. When the discrepancy between the second clock signal and the presettable clock signal has been evaluated, the digital control circuit calculates a value that is written to the second register. The second register acts directly on the operation of the programmable digital frequency divider, whose division ratio is set by the value stored in the second register.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a circuit configuration for resynchronizing a clock signal, it is nevertheless not intended to be limited to the details shown, because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 4903283 (1990-02-01), Eisenberg
patent: 5926048 (1999-07-01), Greatwood
patent: 6316974 (2001-11-01), Traci et al.
patent: 6404161 (2002-06-01), Roubinet et al.
patent: 37 19 582 (1988-12-01), None
Non-Patent Document “Electronic Circuits” (Tietze et al.), Springer Verlag, pp. 860-870.
Jenkner Christian
Nössing Gerhard
Ghebretinsae Temesghan
Mayback Gregory L.
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