Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
1998-12-09
2004-11-30
Lee, Hsien Ming (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C257S501000, C257S506000, C257S510000, C438S221000, C438S296000, C438S424000, C438S426000, C438S701000, C438S713000
Reexamination Certificate
active
06825544
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to isolation structures for integrated circuits, and more particularly to shallow trench isolation methods and structures.
BACKGROUND OF THE INVENTION
Integrated circuit devices typically include a number of active devices, such as transistors, that are separated from one another by isolation structures. Isolation structures help to ensure that active devices can be individually controlled by preventing current flow between adjacent devices. Without sufficient isolation, leakage paths can occur between active devices, leading to a number of undesirable effects. Such undesirable effects can include increased power dissipation, increased susceptibility to latch-up, unstable logic states, and decreased noise margins.
Integrated circuits are often manufactured with generational decreases in device sizes. That is, while an initial manufacturing process may be capable of fabricating active devices with an initial minimum feature size, as processing technology progresses, the minimum size continues to decrease. As just one example, a process may initially be capable of fabricating insulated gate transistors having a minimum gate length of 0.5 microns (&mgr;m). With improvements in process technology, smaller gate lengths are possible. For example, gate lengths of 0.25 or 0.21 &mgr;m can be achieved.
Decreases in minimum active device size can result in integrated circuit devices designs being subjected to generational “shrinks.” Generational shrinks involve using an existing basic design, but then shrinking the structures within the design according to process improvements. Each shrink can result in an integrated circuit having an overall smaller physical size. Smaller integrated circuit sizes allow more integrated circuits to be fit on a wafer, which can result in a more cost-effective production.
While process improvements can allow for the shrinking of certain device structures, other device structures are not always capable of being reduced in size. In particular, as device features (“geometries”) continue to shrink, it can be increasingly more difficult to achieve a corresponding shrink in an isolation structure.
One type of isolation structure that is commonly employed in integrated circuits that are fabricated on a silicon substrate, is the local oxidation of silicon “LOCOS.” LOCOS involves placing a barrier layer (silicon nitride for example) over the semiconductor substrate. Openings are then formed in the barrier layer. The exposed portion of the silicon substrate is oxidized to create a silicon dioxide “field oxide.” The field oxide has tapered edges (“bird's beak”) that extend under edges of the barrier layer, encroaching into the active portions of the substrate. The encroachment can result in larger isolation structures in the lateral direction (parallel to the semiconductor substrate). For this reason, LOCOS-type isolation can be undesirable.
In addition to extending in a lateral direction, LOCOS structures can extend in the vertical direction, above the substrate. Consequently, LOCOS structures can add to the topography of semiconductor device. Additional topography can be undesirable as it can complicate subsequent patterning step. Furthermore, because LOCOS is essentially “grown” in the oxide, smaller lateral dimensions correspond to smaller vertical dimensions. Accordingly, while LOCOS structures having smaller lateral features can be formed, such structures will have very small vertical depth. LOCOS structures having too small a vertical depth, provide less reliable isolation, and are more susceptible to functioning as a parasitic transistor, in the event a conductive line is situated over the LOCOS structure.
An alternative to LOCOS, and LOCOS-type isolation is shallow trench isolation (STI). Conventional STI approaches involve etching a trench into a substrate, and then filling the trench with an isolation material. In this way, lateral and vertical dimensions of an isolation structure can be established by an etch step. While conventional STI approaches can result in smaller isolation structures, such approaches can have drawbacks. To better understand these drawbacks, a conventional STI method and associated structure will now be described.
Referring now to
FIG. 1
, a flow diagram is set forth that describes a conventional STI method. The conventional STI method is used to form an isolation structure in a silicon substrate. The method set forth in the flow diagram is designated by the general reference character
100
and is shown to include a number of steps, each of which involves one or more fabrication steps.
FIGS. 2A-2G
are side cross-sectional views illustrating the formation of a conventional STI structure made according to the method set forth in FIG.
1
.
The flow diagram
100
is shown to include a “Thin Oxide/Nitride Deposition” step
102
. Step
102
involves forming a thin silicon dioxide (“oxide”) layer on a silicon substrate, and then depositing a silicon nitride (“nitride”) layer over the oxide layer.
FIG. 2A
sets forth a side cross-sectional view of a conventional STI structure following step
102
. The STI structure is designated by the general reference character
200
, and is shown to include a silicon substrate
202
. A relatively thin layer of oxide
204
has been formed on the silicon substrate
202
. Deposited over the relatively thin layer of oxide
204
is a layer of nitride
206
.
Following step
102
, the STI flow diagram
100
continues with a “Photo Pattern” step
104
. Step
104
involves forming an etch mask over the nitride layer using photolithographic steps. A side cross-sectional view of the STI structure
200
following step
104
is set forth in FIG.
2
B. The resulting etch mask is shown to include developed photoresist (“resist”)
208
formed over an anti-reflective coating (ARC)
210
. The ARC
210
can reduce corner reflections that result in unwanted rounding of pattern corners or other undesirable results. An etch mask opening
212
is formed within the resist
208
and the ARC
210
, resulting in a portion of the nitride layer
206
being exposed.
Following step
104
, the conventional STI flow diagram
100
continues with a “Nitride Etch (stop on oxide)” step
106
. Step
106
involves applying a silicon nitride etch that results in the removal of that portion of the nitride layer that is exposed by the resist pattern
208
. A side cross-sectional view of the STI structure
200
following step
106
is set forth in FIG.
2
C. The opening
212
following the silicon nitride etch is shown to extend through the nitride layer
206
to the relatively thin oxide layer
204
. Also set forth in
FIG. 2C
, by dashed lines, are residual nitride “particles”
214
within the etch mask opening
212
. Such particles can arise despite concerted efforts to have as clean a process as possible.
Following step
104
, the STI flow diagram
100
continues with a “Si Etch (Form the trench in Si substrate)” step
108
. Step
108
involves applying a silicon etch.
FIG. 2D
sets forth a side cross-sectional view of the STI structure
200
following step
108
. The silicon etch has formed a silicon trench
216
below the etch mask opening
212
. Also set forth in
FIG. 2D
, by dashed lines, are “micro-masking” defects
218
arising from the particles
214
formed in the previous nitride etch step. The nitride particles
214
function essentially as etch masks during the silicon etch, and can result in undesirable uneven topography in the bottom of a silicon trench, including silicon “pillars.”
Following the silicon etch (step
108
), a “Liner Oxidation” step
110
is performed. Liner oxidation involves forming a relatively thin layer of oxide on the exposed surfaces of a trench in the silicon substrate.
FIG. 2E
sets forth a side cross-sectional view of the STI structure
200
following step
110
. The resulting thin oxide layer
220
can be considered a “liner oxide,” as it lines the vertical and horizontal surfaces within the trench
216
. As shown by dashed lines in
FI
Cypress Semiconductor Corporation
Lee Hsien Ming
Sako Bradley T.
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