Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-05-15
2004-10-19
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185020, C365S185110
Reexamination Certificate
active
06807103
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electrically erasable and programmable memories, and more particularly to page-erasable FLASH memories.
BACKGROUND OF THE INVENTION
Currently, the market of electrically erasable and programmable memories in integrated circuits mainly comprises EEPROM memories and FLASH memories (or FLASH-EEPROM). EEPROM memories can be word programmable and erasable or page programmable and erasable. For technological reasons, FLASH memories (or FLASH-EEPROM) are generally word programmable and sector erasable, one sector generally comprising many pages.
As background,
FIG. 1
schematically represents a FLASH memory array comprising a plurality of memory cells CF
i,j
arranged as a matrix and connected to word lines WL
i
and bit lines BL
j
. The cells CF
i,j
of the FLASH memory are very simple in structure and only comprise one floating-gate transistor FGT, here an NMOS transistor, having its gate G connected to a word line WL
i
, its drain D connected to a bit line BL
j
and its source S connected to a source line SL
i
. The bit lines BL
j
are grouped together by columns of rank k to form binary words W
i,k
comprising for example eight cells CF
i,j
each (bytes), the cells of a single word W
i,k
possibly being adjacent (as represented in
FIG. 1
) or interlaced with cells belonging to other words. A physical page P
i
of the FLASH memory is formed by all the memory cells C
i,j
connected to a single word line WL
i
, and thus comprises a plurality of binary words W
i,k
. A sector is formed by a set of pages P
i
the source lines SL
i
of which are interconnected and are always at the same electric potential.
In such a FLASH memory, the programming of a cell involves injecting electric charges into the floating gate by hot electron injection effect while the erasing of a cell involves extracting electric charges trapped in the floating gate by tunnel effect. An erased transistor FGT has a positive threshold voltage VT
1
of low value and a programmed transistor has a threshold voltage VT
2
higher than VT
1
. When a read voltage V
READ
that is between VT
1
and VT
2
is applied to its gate, an erased transistor is on, which corresponds by convention to the reading of a logic “1”, and a programmed transistor remains off, which corresponds by convention to the reading of a logic “0”.
Due to the simplicity of their memory cells, which do not comprise access transistors as in EEPROM memories, FLASH memories have the advantage of being very compact in terms of silicon surface occupied and therefore have, for a constant silicon surface, a storage capacity that is much greater than that of EEPROM memories, for a lower cost price. However, they are less flexible to use due to the need to simultaneously erase all the memory cells of a single sector.
In certain applications, it is however desirable to benefit from the advantages of FLASH memories (compactness and cost price) while benefiting from the possibility of erasing by page, for example when the data to be logged are small in volume and the erasure of an entire sector before programming a page cannot be considered. However, finding a page-erasable FLASH memory involves certain difficulties.
To understand the problem posed, it will first be reminded that a memory cell can be erased according to the source erase method or the channel erase method. The source erase method, referring to
FIG. 1
, involves applying a positive erase voltage V
ER+
in the order of 4 to 5V to all the source lines SL
i
of a single sector, while the word lines WL
i
of the sector considered receive a negative erase voltage V
ER−
in the order of −8V, the material forming the channel of the transistors (substrate or well) being grounded. The effect of the difference in potential appearing between the source S and the gate G of the transistors is to force out the electric charges trapped in the floating gates (by tunnel effect) and to erase the transistors. The negative voltage V
ER−
is applied to the gates of all the transistors of a single sector by inhibiting a word line decoder XDEC (FIG.
1
), which receives the voltage V
ER−
at one input and applies it to all the word lines WL
i
of the sector to be erased regardless of the address received at input. Simultaneously, all the outputs of a column decoder YDEC connected to the bit lines BL
j
are taken to high impedance.
The channel erase method can be distinguished from the source erase method by the fact that the positive erase voltage V
ER+
is applied to the sources of the transistors through the material forming the channel regions (substrate or well) to which a bias voltage V
B
is applied. The junctions PN existing between the channel regions and the source regions are biased in the forward direction and the voltage V
B
is passed onto all the sources of the transistors of a single sector to form the voltage V
ER+
. At the same time, the negative erase voltage V
ER−
is, as above, applied to the gates of the transistors through the word line decoder XDEC that is in the inhibited state.
The advantage of a channel erase method is that the channel regions and the source regions are at substantially the same electric potential, the channel/source junction diodes being biased in the forward direction. Compared to a source erase method, there is therefore no longer any leakage current in the source/channel direction. The erase voltage V
ER+
can be taken to a higher potential than in the case of a source erase method, such as 8 to 10V for example against 4 to 5V in the first case.
One known approach for producing a page-erasable FLASH memory involves equipping each source line SL
i
with a select transistor allowing for a selective application of the erase voltage V
ER+
. This approach is in accordance with the teaching disclosed by the patent EP 704 851 and the application WO 98/33187, in which the selective erasure of a word is obtained by equipping the cells of a single word with a source select transistor.
However, this approach has various disadvantages. Firstly, a FLASH memory cell is programmed with a considerable drain-source current. As a result, in the event of simultaneous programming of all the cells of a word, a high current is collected by the select transistor of the source line. This current leads to an increase in the drain-source voltage of the select transistor, a corresponding reduction in the drain-source voltage of the floating-gate transistors, and an increase in the programming time. The cells of a single word must therefore be programmed individually, or jointly with cells belonging to other binary words (WO 98/33187). Furthermore, providing source line select transistors is not compatible with the channel erase method. In fact, as the erase voltage V
ER+
is, in this case, applied through the material forming the channel, providing source line select transistors does not prevent the voltage V
ER+
from reaching the sources of transistors and from creating an electric field leading to charges trapped in the floating gates being forced out.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method for selectively erasing one page of FLASH memory that does not require providing source line select transistors.
Another object of the present invention is to provide a method for selectively erasing one page of FLASH memory that is compatible with the channel erase method.
Another object of the present invention is to provide a page-programmable FLASH memory that is protected against a possible alteration of the threshold voltage of its floating-gate transistors, due in particular to the implementation of a selective page-erase method according to the present invention.
Therefore, the present invention provides a method for logging data in a FLASH memory comprising at least one sector, wherein the erasing of a page from the memory comprises applying a negative erase voltage to the gates of the floating-gate transistors of the page to be er
Cavaleri Paola
Devin Jean
Leconte Bruno
Zink Sebastien
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Le Vu A.
STMicroelectronics S.A.
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