Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-09-21
2004-08-24
Sherry, Michael (Department: 2838)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
06781805
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-268714, filed Sep. 22, 1999; and No. 2000-278705, filed Sep. 13, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to protection for ESD (Electro Static Discharge) of a semiconductor device, particularly, to a protection circuit against an ESD surge and an external excess voltage using a stacked MOSFET structure.
In the conventional protection circuit of a semiconductor device, a discharging circuit consisting of combination of a diode and a resistor is formed between the input pad and the ground or between the output pad and the ground so as to discharge the static charge accumulated in the pins of the package in the assembling and mounting procedure so as to prevent the electrostatic breakdown.
On the other hand, the scaling is a very effective means for the high integration degree and the high operating speed of an LSI. In accordance with the scaling of the process, the operation voltage is also subjected to the scaling in view of the voltage tolerance.
However, the I/O interface voltage is slow in the progress of the scaling of the power source voltage, compared with the device, with the result that it is highly required that the low operating voltage and the high I/O interface voltage be satisfied simultaneously. An I/O formation technology tolerant to other power sources is known to the art as a technology that satisfies this requirement without giving rise to a process overhead.
In general, in the case of using an output buffer, the external voltage is higher than the internal operation voltage so as to give rise to a problem in respect of the reliability of the gate insulating film. In other words, a reliability problem represented by TDDB (Time-Dependent Dielectric Breakdown) and HCI (Hot Carrier Injection) tends to be generated.
In order to overcome the problem noted above, it was customary in the past to use a protection technology utilizing a stacked structure of MOSFFT's, as shown in FIG.
1
A. For the sake of simplicity, N-channel MOSFET's alone are stacked in the circuit shown in FIG.
1
A. As shown in the drawing, N-channel MOSFET's Q
1
and Q
2
are connected in series between a pad
1
of an external power source Vext and the ground (GND) so as to form a stacked structure of MOSFET's. An internal power source Vint is applied to an internal voltage terminal
2
connected to the gate of the MOSFET Q
1
. Incidentally, voltage of 0V to Vint is applied to the terminal
2
a
connected to the gate of the MOSFET Q
2
.
In the case of using the stacked structure of MOSFET's shown in
FIG. 1A
, the gate-drain voltage VGD of the MOSFET and the gate-source voltage VGS of the MOSFET is lower than Vint, i.e., VGD, VGS<Vint, so as to assure the TDDB reliability. Further, since the drain-source voltage VDS divides Vext, the HCI reliability is also ensured.
Concerning the MOSFET Q
2
, the drain voltage is held at Vint−Vth, where Vth represents the threshold voltage, so as to avoid the problem in terms of the reliability.
In recent years, in a semiconductor device using a different power source technology provided with the external power source Vext and the internal power source Vint, a protection circuit of I/O's tolerant to other power sources having a stacked structure of MOSFET's in which the MOSFET's Q
1
and Q
2
are connected in series between the pad
1
and GND is used as a protection circuit exhibiting a high surge tolerance against the surge entering through, for example, the pad
1
, as shown in
FIGS. 1A and 1B
.
FIG. 1B
shows the equivalent circuit of FIG.
1
A and the problem in the case where a surge voltage V is applied to the pad
1
for a short time. The external surge voltage V enters the pad
1
for various reasons. For example, the external surge voltage is generated in the case of ESD in which the charge added to the surrounding portions in the assembling, testing and mounting steps to a system is discharged through the pins of the package.
In the structure shown in
FIGS. 1A and 1B
, it is possible for the breakdown of the protection circuit to take place in the case where the surge voltage V is applied for a short time to the pad
1
. To be more specific, under the state that, although the gate of the MOSFET Q
1
is connected to Vint, the power source is not turned on as shown in
FIG. 1A
, the gate of the MOSFET Q
1
bears the ground potential. In addition, since a very large equivalent capacitance is connected to Vint, the gate-drain voltage VGD of the MOSFET Q
1
exceeds the withstand voltage of the gate insulating film during application of the surge voltage V. As a result, the MOSFET Q
1
is broken down before the snap-back characteristics of the MOSFET effective for the surge absorption perform their functions.
The breakdown process of the MOSFET Q
1
during application of the surge voltage V to the pad
1
will now be described with reference to the equivalent circuit shown in FIG.
1
B. If the surge voltage V is applied to the equivalent circuit shown in
FIG. 1B
, the electron-hole avalanche takes place on the channel surface on the drain side of the MOSFET Q
1
. As a result, a large current flows between the source and drain of the MOSFET Q
1
, and the surge voltage applied to the external power source pad
1
is rapidly lowered by the discharge current. It follows that the stacked MOSFET protection circuit exhibits excellent snap-back characteristics.
However, since a high surge voltage V is applied to the stacked MOSFET protection circuit consisting of the MOSFET's Q
1
and Q
2
, the greatest gate-drain voltage VGD is applied to the drain edge portion of the gate insulating film of the MOSFET Q
1
as denoted by a circle
10
of a broken line in
FIG. 1B
, giving rise to the problem that the gate insulating film is broken down at the portion denoted by the broken circle
10
.
On the other hand, it was attempted to use a protection circuit of one stage MOSFET in which the drain of the MOSFET Q
2
is connected directly to the pad
1
. In the protection circuit of one stage MOSFET, the drain voltage of the MOSFET Q
2
is lowered by an amount equal to the source-drain voltage of the MOSFET Q
1
so as to lower the maximum gate-drain voltage VGD applied to the drain edge of the gate insulating film of the MOSFET Q
2
so as to suppress the breakdown of the gate insulating film.
FIG. 2
compares the snap-back characteristics of the stacked MOSFET protection circuit consisting of the MOSFET's Q
1
and Q
2
with those of protection circuit of the one stage MOSFET consisting of the MOSFET Q
2
alone.
In
FIG. 2
, the snap-back voltage of the stacked structure is denoted by V
SB
, which is denoted by a thick broken line, the drain voltage in the “ON” state is denoted by V
DB
. The phenomenon called in general a second breakdown causes the snap-back curves in the transition region in which V
SB
is switched to V
DB
to show two steps.
On the other hand, the snap-back voltage V
SB
, and the drain voltage V
DB
, under the “ON” state for the one stage MOSFET, which are denoted by a thin solid curve, are lower than the snap-back voltage V
SD
and the drain voltage V
DB
under the “ON” state, respectively, for the stacked MOSFET structure, which are denoted by a thick broken curve.
If the surge voltage V caused by, for example, ESD is applied to the pad
1
, the protection circuit is repeatedly switched along the curves of the snap-back characteristics shown in
FIG. 2
, with the result that the protection circuit is capable of performing the surge protection of the semiconductor integrated circuit until the breakdown
10
of the gate insulating film shown in
FIG. 1B
is made unrecoverable.
As described previously, the snap-back voltage V
SB
, of the conventional one stage MOSFET protection circuit is lower than the snap-back voltage V
SB
of the protection circuit
Laxton Gary L
Sherry Michael
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