Method of manufacturing chip scale package

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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C029S827000, C029S830000, C029S832000, C257S666000

Reexamination Certificate

active

06735859

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device assemblies. More particularly, the invention pertains to a method for producing a chipon-board semiconductor device assembly with a heat spreading/dissipating member, and the device produced thereby.
2. State of the Art
In the design and production of modem integrated circuits (IC), an important consideration is the dissipation of heat generated in the semiconductor device. Elevated temperatures may cause irreparable damage to the die and its electrical connections.
Various methods for preventing excessive temperatures in a semiconductor device have been in use.
Thus, for low-power devices of less than about 1 watt, the metal lead frame itself may be sufficient to dissipate generated heat. Lead frame configurations for improved heat dissipation are shown in U.S. Pat. No. 5,541,446 of Kierse, U.S. Pat. No. 4,961,107 of Geist et al., and U.S. Pat. No. 5,101,465 of Murphy.
For higher power packaged devices, a metal heat spreader may be incorporated into the package or attached to the outside of the package. Because of the generally low thermal conductivity of polymers, the heat dissipation design is more critical for polymer-packaged devices than for those packaged in ceramic or metal.
The use of heat spreaders/heat sinks/heat dissipaters in packaged semiconductor devices are often used to conduct heat to the exterior of the devices, either directly or via the leads. A wide variety of such is illustrated in U.S. Pat. No. 5,596,231 of Combs, U.S. Pat. No. 5,594,282 of Otsuki, U.S. Pat. No. 5,598,034 of Wakefield, U.S. Pat. No. 5,489,801 to Blish II, U.S. Pat. No. 4,024,570 of Hartmann et al., U.S. Pat. Nos. 5,378,924 and 5,387,554 of Liang, U.S. Pat. No. 5,379,187 of Lee et al., U.S. Pat. No. 4,507,675 of Fujii et al., U.S. Pat. No. 4,642,671 of Rohsler et al., U.S. Pat. No. 4,931,852 of Brown et al., U.S. Pat. No. 5,173,764 of Higgins III, U.S. Pat. No. 5,379,186 to Gold et al., U.S. Pat. No. 5,434,105 to Liou, and U.S. Pat. No. 5,488,254 to Nishimura et al.
The above-indicated references may be characterized as providing complex devices requiring difficult and/or costly processes to achieve the desired heat dissipation. Most of the references are not applicable at all to a high density device attached in a bare state to a substrate such as a circuit board.
Encapsulation compositions and methods are shown in U.S. Pat. No. 4,358,552 to Shinohara et al. and U.S. Pat. No. 5,194,930 to Papathomas et al.
SUMMARY OF THE INVENTION
The present invention comprises a high density semiconductor device assembly for electrical connection without wires to a substrate such as a circuit board. In a preferred embodiment, the invention comprises a chip-on-board (COB) device with a heat spreader/dissipater on its back side. The active surface on its “front side” may be attached in a bare die state to the substrate by lead bond methods known in the art, preferably by ball-grid-array (BGA) methods which simultaneously complete each of the conductive bonds between die and circuit board.
The present invention also encompasses a “paddle frame” strip for (a) providing a heat spreader/dissipater on each die, (b) supporting the dice for die testing and/or (c) supporting the dice for applying conductive bumps to the bond pads. The paddle frame strip may incorporate any number of paddle frames, and preferably has at least eight paddle frames.
The present invention further comprises a method for producing the high density semiconductor device with the heat spreader/dissipater.
The present invention provides significant advantages in the production of dense semiconductor devices, including enhanced reliability, ease of production, and reduced production costs.


REFERENCES:
patent: 4024570 (1977-05-01), Hartmann et al.
patent: 4143456 (1979-03-01), Inoue
patent: 4264917 (1981-04-01), Ugon
patent: 4300153 (1981-11-01), Hayakawa et al.
patent: 4358552 (1982-11-01), Shinohara et al.
patent: 4507675 (1985-03-01), Fujii et al.
patent: 4642671 (1987-02-01), Rohsler et al.
patent: 4931852 (1990-06-01), Brown et al.
patent: 4961107 (1990-10-01), Geist et al.
patent: 5101465 (1992-03-01), Murphy
patent: 5173764 (1992-12-01), Higgins, III
patent: 5194930 (1993-03-01), Papathomas et al.
patent: 5214845 (1993-06-01), King et al.
patent: 5233220 (1993-08-01), Lamson et al.
patent: 5378924 (1995-01-01), Liang
patent: 5379186 (1995-01-01), Gold et al.
patent: 5379187 (1995-01-01), Lee et al.
patent: 5387554 (1995-02-01), Liang
patent: 5434105 (1995-07-01), Liou
patent: 5436203 (1995-07-01), Lin
patent: 5450283 (1995-09-01), Lin et al.
patent: 5488254 (1996-01-01), Nishimura et al.
patent: 5489538 (1996-02-01), Rostoker et al.
patent: 5489801 (1996-02-01), Blish, II
patent: 5490324 (1996-02-01), Newman
patent: 5528076 (1996-06-01), Pavio
patent: 5541446 (1996-07-01), Kierse
patent: 5550408 (1996-08-01), Kunitomo et al.
patent: 5559306 (1996-09-01), Mahulikar
patent: 5594282 (1997-01-01), Otsuki
patent: 5596231 (1997-01-01), Combs
patent: 5598034 (1997-01-01), Wakefield
patent: 5606199 (1997-02-01), Yoshigai
patent: 5661086 (1997-08-01), Nakashima et al.
patent: 5708567 (1998-01-01), Shim et al.
patent: 5773896 (1998-06-01), Fujimoto et al.
patent: 5884396 (1999-03-01), Lin
patent: 5907769 (1999-05-01), Corisis
patent: 6163956 (2000-12-01), Corisis
patent: 6314639 (2001-11-01), Corisis

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