Semiconductor device manufacturing: process – Chemical etching – Altering etchability of substrate region by compositional or...
Reexamination Certificate
2001-07-27
2004-08-10
Deo, Duy-Vu (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Altering etchability of substrate region by compositional or...
C438S719000, C438S720000, C438S723000, C438S724000, C216S062000, C216S081000
Reexamination Certificate
active
06774043
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it relates to a method of forming a work pattern including resist pattern formation utilized for manufacturing a semiconductor integrated circuit device, particularly a resist pattern forming step effective for obtaining high dimensional accuracy and alignment accuracy of a wiring pattern or the like having a line width of not more than 0.20 &mgr;m.
2. Description of the Background Art
When manufacturing a semiconductor integrated circuit (semiconductor device) at present, selective working is performed on an underlayer such as a semiconductor substrate through etching or ion implantation. In this case, a pattern of a composition sensitized by active rays such as ultraviolet rays, X-rays or electron rays, i.e., the so-called photosensitive resist coating (hereinafter simply referred to as “resist film”) is formed on the underlayer, in order to selectively protect a worked portion of the underlayer.
The most generally employed method of forming a resist pattern is carried out through application of ultraviolet rays employing a stepping projection aligner (stepper) having a light source of a mercury lamp for g rays (wavelength: 436 nm) or i rays (wavelength: 365 nm), a KrF excimer laser (wavelength: 248 nm) or an ArF excimer laser (wavelength: 193 nm).
A photomask is mounted on the stepper for performing exposure, while the photomask, referred to as a reticle, obtained by forming a circuit pattern on a glass substrate with a shielding film of chromium (Cr) or the like must be precisely aligned (overlaid) for correctly setting positional relation between the photomask and a circuit pattern already formed on the substrate.
The pattern drawn on the photomask is contracted through a lens and transferred to the resist film applied to the semiconductor substrate. Thereafter the resist film is developed thereby enabling formation of a resist pattern.
It is assumed that this resist pattern forming step must be repeated by about 20 to 30 times in general, in order to manufacture a semiconductor integrated circuit device.
The degree of integration and the performance of a semiconductor integrated circuit are increasingly improved in recent years, followed by requirement for further refinement of a circuit pattern. In relation to a DRAM (dynamic random access memory), for example, a resist pattern having a line width of 0.20 to 0.18 &mgr;m is drawn on a 64-Mbit DRAM subjected to mass production at present, and a KrF excimer laser beam (&lgr;=248 nm) is most generally utilized in a photolithography step therefore among ultraviolet rays. Further refinement of the pattern as well as improvement of dimensional accuracy and alignment accuracy are required for the future.
While a work pattern such as a wiring pattern is obtained by etching an underlayer film through a mask of a resist pattern, it has recently been recognized that there is such space width dependency (pattern density dependency) in formation of the work pattern that a critical dimension shift (the quantity of displacement from a resist pattern) resulting from dry etching varies with the space width of a region adjacent to the work pattern.
In other words, it has been recognized that the critical dimension shift on a rough region having a relatively large space width differs from that on a dense region having a relatively small space width on the work pattern. The difference between the critical dimension shift on the rough region having a relatively large space width and that on the dense region having a relatively small space width is hereinafter referred to as “critical dimension shift density difference”.
This means that the dimensional accuracy of the work pattern is deteriorated in etching due to the space width dependency, while the critical dimension shift density difference is reaching an unignorable level following pattern refinement.
In particular, it is also recognized that large critical dimension shift density difference results from etching of a silicon oxide film or a silicon nitride film. However, the pitch of wires and the space between the wires and contact holes are increasingly narrowed due to the refinement and densification of the pattern and a self-aligned contact hole structure is generally employed. Therefore, a device structure obtained by stacking an insulator film such as a silicon oxide film or a silicon nitride film on a metal wiring film is requisite also in a gate forming step.
Therefore, a method of suppressing critical dimension shift density difference resulting from etching of the insulator film is necessary.
FIGS. 48
to
51
are sectional views showing an exemplary conventional wiring pattern forming method. The conventional wiring pattern forming method is now described with reference to
FIGS. 48
to
51
.
First, a polysilicon layer
2
is formed on a silicon substrate
1
in a thickness of 50 nm (500 Å), then a silicon nitride film
3
is formed in a thickness of 165 nm (1650 Å), and thereafter a photoresist film
4
is applied and prebaked at 100° C. for 90 seconds, as shown in FIG.
48
. At this time, the revolution speed in application is so adjusted that the thickness of the photoresist film
4
is 585 nm (5850 Å).
Then, exposure is performed with a stepper having a KrF excimer laser (wavelength: 248 nm)
6
as a light source through a reticle (photomask)
5
on which wiring patterns are drawn at various pitches, as shown in FIG.
49
. Off-axis illumination employing a ⅔ annular illumination aperture is applied under an illumination condition of NA (numerical aperture) =0.55.
Then, post-exposure baking (PEB) is performed at 110° C. for 90 seconds and thereafter development is performed for 60 seconds with an aqueous solution of 2.38 percent by weight of tetramethylammonium hydroxide (TMAH), thereby obtaining a resist pattern
4
a
responsive to the reticle
5
as shown in FIG.
50
.
Then, the resist pattern
4
a
is employed as a mask for etching the nitride film
3
and the polysilicon layer
2
through a parallel plate reactive ion etcher performing RIE (reactive ion etching) with a gas mixture of trifluoromethane (CHF
3
), tetrafluoromethane (CF
4
), argon (Ar) and oxygen (O
2
), thereby obtaining a wiring pattern (polysilicon pattern
2
a
and silicon nitride pattern
3
a
) as shown in FIG.
51
.
FIG. 52
is a graph showing results of comparison of pattern sizes of the resist pattern
4
a
and a work pattern (multilayer structure of the polysilicon layer
2
and the silicon nitride film
3
) obtained after etching.
FIG. 52
plots the sizes (Line Width) of the resist pattern
4
a
and the work pattern subjected to etching, with reference to a line width of 0.24 &mgr;m, with respect to space widths (Space) respectively.
FIG. 53
is a graph showing space width dependency based on FIG.
52
. This graph shows dependency of critical dimension shift (CD (critical dimension) Shift) in etching at the line width of 0.24 &mgr;m shown in
FIG. 52
on the space width of an adjacent region. Referring to
FIG. 53
, critical dimension shift density difference &Dgr; CD
0
indicating the difference between critical dimension shifts of a densest pattern region and an isolated line pattern region having a sufficiently wide space is about 0.141 &mgr;m.
As shown in
FIG. 53
, the critical dimension shift of a line pattern under rough environment is so large that sizing is necessary for narrowing a mask size from an original design size, in order to finish the isolated line pattern in response to the design. However, process tolerance such as exposure tolerance or focus tolerance (DOF: depth of focus) is narrowed as the mask size and the obtained resist pattern size are reduced, and hence it is undesirable that critical dimension shift density difference resulting from etching is large.
Therefore, it is important to suppress the critical dimension shift in dry etching, particularly space width dependency (p
Tsujita Kouichirou
Yamaguchi Atsumi
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