Process variation resistant self aligned contact etch

Details Process variation resistant self aligned contact etch Process variation resistant self aligned contact etch

2002-08-22

2004-04-06

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000

Reexamination Certificate

active

06716766

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method for etching contacts through layers of an integrated circuit and, in particular, to a self aligned contact (SAC) etch using a multi-step process.
BACKGROUND OF THE INVENTION
The current semiconductor industry poses an ever-increasing pressure for achieving higher device density within a given die area. This is particularly true in memory circuit fabrication, for example, in the manufacture of dynamic random access memory (DRAM). Each memory cell of a DRAM typically consists of a single capacitor and a field effect transistor (FET), which is used as a charge transfer transistor. Binary data is stored as electrical charge on the capacitor in the individual memory cells. In recent years, the number and density of these memory cells on the DRAM chip has dramatically increased so that the number of memory cells on a single chip is expected to soon reach 1 Gigabit.
The increase in circuit density is the result of scaling the individual semiconductor devices (e.g., FETs and capacitors) and increasing device packing density. The reduction in device size is due partly to the advances in photolithography and directional (anisotropic) plasma etching. The increase in device density, however, places increasing demands on many aspects of the fabrication process. For example, alignment of features from one level to the next is of critical importance, particularly the alignment of contact holes with underlying structures, such as an active area, with which they are to connect. The miniaturization of the devices makes the formation of interconnect structures difficult because maintaining sufficient electrical communication requires that the interconnect structure is formed in exact alignment with an underlying active region. At the same time, the area of the interconnect structure interfacing with the active area must be maximized. Thus, as device sizes shrink there is less room for misalignment errors of the interconnect structure.
As the horizontal device feature sizes continue to shrink to submicrometer dimensions, it is necessary to use self-alignment techniques to relax the alignment requirements and improve critical dimension (CD) control. One such technique is called a self-aligned contact (SAC) etch, in which a pair of adjacent gates of the FETs of a pair of memory cells are utilized to align an etched opening in an insulating layer.
FIG. 1
depicts a conventional memory cell construction for a DRAM at an intermediate stage of the fabrication. A pair of memory cells having respective access transistors are formed within a substrate. N-type active regions
116
are provided in a doped p-type well
112
of substrate
110
(for NMOS transistors) and the pair of access transistors have respective gate stacks
130
. The gate stacks
130
include nitride spacers
132
and nitride caps
134
formed to protect the gate stacks
130
and provide an etch stop layer for the SAC etch. An insulating layer
124
of, for example, a borophosphosilicate glass (BPSG), has been applied over the substrate and transistor structures and a mask layer
126
having openings for etching the insulating layer to form contact openings to active regions
116
are also shown. Theoretically, the mask
126
is properly aligned to enable a SAC etch of the insulating layer
124
to provide contact openings down to the active regions
116
.
The SAC etch processes primarily involve dry etches or plasma etches. Almost all of the current dry etch technology for SAC etch processes uses a C
x
F
y
(x>1)-type plasma chemistry, such as, for example, C
4
F
8
, C
5
F
8
, or C
4
F
6
, in combination with other diluent gases. The C
x
F
y
type chemistry is favored because it offers very high selectivity to the silicon nitride cap and silicon nitride spacers, which are the most typical etch stop material for gate stack protection in a SAC etch. However, it has the disadvantage that the conventional SAC etch parameters have a very small process window. This is primarily due to the fact that the C
x
F
y
-type chemistry generates a fluorocarbon polymer which is more carbon rich than the polymers generated with other types of chemistry. With this very carbon-rich fluorocarbon polymer, the etch often results in etch stop condition, a situation when etching stops before reaching the substrate, when the gas flow or temperature is off even by a small amount from the optimal setting.
Conventional approaches to this issue generally attempt to minimize the deposition of polymer, while still maintaining the etch selectivity and controlling overetching conditions to ensure completion of the SAC etch. That is, conventional SAC etch processes try to balance etch chemistry and etch conditions to thoroughly etch through the BPSG, but does not etch the silicon nitride spacers
132
and caps
134
of the gate stacks
130
, and does not deposit enough polymer to cause an etch stop condition prior to exposing the active region. This has been accomplished by varying the chemistry and process parameters, such as the gas phase chemistry through adjustments in the plasma reactor gases or the operating pressure. However, as previously mentioned, to perform an adequate SAC etch using conventional methods, the process parameters must be maintained within a very narrow range. Therefore, there is a need for an alternative etching process that can maintain selectivity to nitride regions while allowing for variations in process parameters.
SUMMARY OF THE INVENTION
The present invention is directed to a method for forming an opening through an interlayer to expose an underlying surface that retains high etch selectivity while having a relatively large process window to accommodate process variations. The method includes masking an interlayer to define an etching area at which the opening is formed, etching the interlayer under a first etching condition through the etching area, and forming a protective layer over portions of exposed surfaces of the opening during etching under the first etching condition. The formation of the protective layer can be performed by utilizing an over-polymerizing etch condition that promotes the formation of a fluorocarbon polymer layer.
The formation of the protective layer continues until an etch stop condition via polymer pinch-off is produced, shutting off etching of the interlayer under the first condition prior to exposing the underlying surface. The method continues with etching through the protective layer under a second etching condition to expose a residual interlayer, and etching the exposed residual interlayer under the second etching condition to expose the underlying surface. The protective layer deposited prior to etching under the second condition shields any underlying structures, resulting in high etch selectivity during the second etch.


REFERENCES:
patent: 5817579 (1998-10-01), Ko et al.
patent: 5948701 (1999-09-01), Chooi et al.
patent: 6028001 (2000-02-01), Shin
patent: 6191042 (2001-02-01), Tsai et al.
patent: 6326312 (2001-12-01), Kim
patent: 6337285 (2002-01-01), Ko
patent: 6372634 (2002-04-01), Qiao et al.

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