Bipolar transistor device having phosphorous

Details Bipolar transistor device having phosphorous Bipolar transistor device having phosphorous

2001-12-10

2004-01-06

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With emitter region having specified doping concentration...

C257S587000

Reexamination Certificate

active

06674149

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to measures for attaining a proper impurity concentration distribution in a heterobipolar transistor or a Bi-CMOS device including a heterobipolar transistor.
BACKGROUND ART
In recent years, a heterobipolar transistor (HBT) has been developed at rapid paces, which is a bipolar transistor formed on a silicon substrate constructed to include a heterojunction structure such as Si/SiGe and Si/SiC to provide superior conduction property and thus enable operation in a higher frequency range. This type of HBT uses a Si/SiGe heterojunction structure formed by epitaxially growing a SiGe layer on a Si substrate. By use of this structure, it becomes possible to attain transistors operating in a high frequency range in which only transistors using a compound semiconductor substrate such as a GaAs substrate can operate so far. Since this HBT includes a Si substrate and a SiGe layer that are made of materials good in compatibility with the general silicon process, it has great advantages of high integrity and low cost. In particular, by forming a HBT and a MOS transistor (MOSFET) on a common Si substrate for integration, a high-performance Bi-CMOS device can be constructed. Such a Bi-CMOS device is promising as a system LSI usable in the communications industry.
As a bipolar transistor constituting the Bi-CMOS device, HBTs including a heterojunction structure such as Si/Si
1-x
Ge
x
and Si/Si
1-y
C
y
have been proposed/prototyped so far. A Si/Si
1-x
Ge
x
HBT, among others, is considered promising from its features including that the band gap can be continuously adjusted using the nature of Si and Ge being solid-soluble to each other in substantially any percentages and the change in band gap with application of strain. For this reason, there have been made a number of proposals on SiGe Bi-CMOS devices in which a MOSFET having only Si layers and a Si/Si
1-x
Ge
x
type HBT are formed on a common Si substrate.
FIG. 12
is a cross-sectional view illustrating a fabrication process of a conventional SiGe Bi-CMOS device. As shown in
FIG. 12
, the upper portion of a Si substrate
500
using the (001) face as the principal plane is occupied by a retrograde well
501
having a depth of 1 &mgr;m containing an n-type impurity such as phosphorus introduced by epitaxial growth, ion implantation, or the like. The concentration of the n-type impurity in a region near the surface of the Si substrate
500
is set to be about 1×10
17
atoms.cm
−3
. As device isolation, provided are a shallow trench
503
with silicon oxide buried therein and a deep trench
504
constructed of an undoped polysilicon film
505
and a silicon oxide film
506
surrounding the undoped polysilicon film
505
. The depths of the trenches
503
and
504
are about 0.35 &mgr;m and about 2 &mgr;m, respectively.
A collector layer
502
is provided in the region of the Si substrate
500
sandwiched by the adjacent trenches
503
. An n
+
collector lead layer
507
for contacting with an electrode of the collector layer
502
via the retrograde well
501
is formed in a region of the Si substrate
500
separated from the collector layer
502
by the shallow trench
503
.
A first buried oxide film
508
having a thickness of about 30 nm, which has a collector opening
510
, is formed on the Si substrate
500
. A Si
1-x
Ge
x
layer
511
b
, composed of an undoped layer (i-Si
1-x
Ge
x
layer) having a thickness of about 20 nm and a p-type impurity doped layer (p
+
Si
1-x
Ge
x
layer) having a thickness of about 40 nm, is formed over the exposed portion of the Si substrate
500
in the collector opening
510
and the first buried oxide film
508
. A Si cap layer
511
a
having a thickness of about 40 nm is then formed on the layer
511
b
. The Si cap layer
511
a
and the Si
1-x
Ge
x
layer
511
b
constitute a Si/Si
1-x
Ge
x
layer
511
. The portion of the Si/Si
1-x
Ge
x
layer
511
located in the collector opening
510
has a single-crystal structure formed by epitaxial growth on the underlying Si substrate
500
, while the portion thereof located on the buried oxide film
508
has a polycrystal structure.
A second buried oxide film
512
having a thickness of about 30 nm is formed on the Si/Si
1-x
Ge
x
layer
511
to serve as an etch stopper. The second buried oxide film
512
has base junction openings
514
and a base opening
518
. A p
+
polysilicon layer
515
having a thickness of about 150 nm is formed burying the base junction openings
514
and expanding over the second buried oxide film
512
, and a third buried oxide film
517
is formed on the p
+
polysilicon layer
515
.
An opening is formed through the portion of the p
+
polysilicon layer
515
and the portion of the third buried oxide film
517
located above the base opening
518
of the second buried oxide film
512
. A fourth buried oxide film
520
having a thickness of about 30 nm is formed on each side face of the p
+
polysilicon layer
515
, and a sidewall
521
made of polysilicon having a thickness of about 100 nm is formed on the fourth buried oxide film
520
. An n
+
polysilicon layer
529
is formed burying the base opening
518
and expanding over the third buried oxide film
517
. The n
+
polysilicon layer
529
functions as an emitter lead electrode. The fourth buried oxide film
520
electrically isolates the p
+
polysilicon layer
515
from the n
+
polysilicon layer
529
, and also blocks diffusion of an impurity from the p
+
polysilicon layer
515
into the n
+
polysilicon layer
529
. Likewise, the third buried oxide film
517
isolates the top surface of the p
+
polysilicon layer
515
from the n
+
polysilicon layer
529
.
Ti silicide layers
524
are formed on the collector lead layer
507
, the p
+
polysilicon layer
515
, and the n
+
polysilicon layer
529
, and sidewalls
523
cover the outer side faces of the n
+
polysilicon layer
529
and the p
+
polysilicon layer
515
. The entire substrate is covered with an interlayer insulating film
525
. Connection holes are formed through the interlayer insulating film
525
to reach the Ti silicide layers
524
on the n
+
collector lead layer
507
, the p
+
polysilicon layer
515
as part of an external base, and the n
+
polysilicon layer
529
as the emitter lead electrode. W plugs
526
bury the connection holes, and metal interconnections
527
connected to the W plugs
526
extend on the interlayer insulating film
525
.
The structure of the emitter-base junction shown in the partial enlarged view in
FIG. 12
will be described. The region of the Si
1-x
Ge
x
layer
511
b
located under the base opening
518
functions as an internal base (intrinsic base)
519
. The region of the Si cap layer
511
a
located immediately under the base opening
518
, which contains boron introduced by diffusion from the n
+
polysilicon layer
529
, functions as an emitter
530
.
The remaining portion of the Si/Si
1-x
Ge
x
layer
511
other than the region under the base opening
518
and the p
+
polysilicon layer
515
constitute an external base
516
. Note that in the partial enlarged view, the portion of the Si/Si
1-x
Ge
x
layer
511
excluding the region under the base opening
518
functions as the external base
516
.
By the construction described above, provided is the Si/SiGe NPN heterobipolar transistor including the n
+
-type emitter
530
made of Si single crystal, the p
+
-type internal base
519
mainly made of Si
1-x
Ge
x
single crystal, and the collector layer
502
made of Si single crystal. Note however that the emitter/base/collector are partitioned from one another, not by the boundaries of Si/SiGe crystals, but by changes of the conductivity type of impurities. Therefore, to be precise, the boundaries of the emitter/base/collector vary depending on the profiles of the impurities. In particular, for applicat

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