Synthetic ripple regulator

Details Synthetic ripple regulator Synthetic ripple regulator

2002-09-06

2004-09-14

Patel, Rajnikant B. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S282000, C323S285000

Reexamination Certificate

active

06791306

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to power supply circuits and components therefor, and is particularly directed to a synthetic ripple regulator for a DC—DC converter. The synthetic ripple regulator of the invention generates an artificial or synthesized ripple waveform that controls the switching operation of the converter, reducing output ripple and improving DC accuracy.
BACKGROUND OF THE INVENTION
Electrical power for integrated circuits is typically supplied by one or more direct current (DC) power sources. In a number of applications the circuit may require plural regulated voltages that are different from the available supply voltage (which may be relatively low e.g., on the order of three volts or less, particularly where low current consumption is desirable, such as in portable, battery-powered devices). Moreover, in many applications the load current may vary over several orders of magnitude. To address these requirements it has been common practice to employ pulse or ripple generator-based converters, such as a hysteresis or ‘bang—bang’ converter of the type shown in FIG.
1
.
Such a ripple regulator-based DC—DC voltage converter employs a relatively simple control mechanism and provides a fast response to a load transient. The switching frequency of the ripple regulator is asynchronous, which is advantageous in applications where direct control of the switching frequency or the switching edges is desired. For this purpose, the ripple regulator of
FIG. 1
employs a hysteresis comparator
10
, that controls a gate drive circuit
20
, respective output drive ports
22
and
23
of which are coupled to the control or gate drive inputs of a pair of electronic power switching devices, respectively shown as an upper P-MOSFET (or PFET) device
30
and a lower N-MOSFET (or NFET) device
40
. These FET switching devices have their drain-source paths coupled in series between first and second reference voltages (Vdd and ground (GND)).
The gate drive circuit
20
controllably switches or turns the two switching devices
30
and
40
on and off, in accordance with a pulse width modulation (PWM) switching waveform (such as that shown at PWM in the timing diagram of
FIG. 2
) supplied by comparator
10
. The upper PFET device
30
is turned on and off by an upper gate switching signal UG applied by the gate driver
20
to the gate of the PFET device
20
, and the NFET device
30
is turned on and off by a lower gate switching signal LG applied by the gate driver
20
to the gate of the NFET device
30
.
A common or phase voltage node
35
between the two power FETs
30
/
40
is coupled through an inductor
50
to a capacitor
60
, which is referenced to a prescribed potential (e.g., ground (GND)). The connection
55
between the inductor
50
and the capacitor
60
serves as an output node, from which an output voltage output (shown as triangular waveform output in
FIG. 2
) is derived. In order to regulate the output voltage relative to a prescribed reference voltage, the output node is coupled to a first, inverting (−) input
11
of the hysteresis comparator
10
, a second, non-inverting (+) input
12
of which is coupled to receive a DC Reference voltage.
In such a hysteretic or ‘bang—bang’ regulator, the output PWM signal waveform produced by hysteresis comparator
10
transitions to a first state (e.g., goes high) when the output voltage Vout at node
55
falls below the reference voltage Reference (minus the comparator's inherent hysteresis voltage &Dgr;); the comparator's PWM output transitions to a second state (e.g., goes low) when the output voltage Vout exceeds the reference voltage plus the hysteresis voltage &Dgr;. The application of or increase in load will cause the output voltage (Vout) to decrease below the reference voltage, in response to which comparator
10
triggers the gate drive to turn on the upper switching device
30
. Because the converter is asynchronous, the gate drive control signal does not wait for a synchronizing clock, as is common in most fixed frequency PWM control schemes.
Principal concerns with this type of ripple regulator include large ripple voltage, DC voltage accuracy, and switching frequency. Since the hysteretic comparator
10
directly sets the magnitude of the ripple voltage Vout, employing a smaller hysteresis &Dgr; will reduce the power conversion efficiency, as switching frequency increases with smaller hysteresis. In order to control the DC output voltage, which is a function of the ripple wave shape, the peak
71
and the valley
72
of the output ripple voltage (Output, shown in
FIG. 2
) is regulated. For the triangular wave shape shown, the DC value of the output voltage is a function of the PWM duty factor. The output voltage wave shape also changes at light loads, when current through the inductor
50
becomes discontinuous, producing relatively short ‘spikes’ between which are relatively long periods of low voltage, as shown by the DISCON waveshape in FIG.
2
. Since the ripple voltage wave shape varies with input line and load conditions, maintaining tight DC regulation is difficult.
In addition, improvements in capacitor technology will change the ripple wave shape. In particular, the current state of ceramic capacitor technology has enabled the equivalent series resistance or ESR (which produces the piecewise linear or triangular wave shape of the output voltage waveform shown in
FIG. 2
) of ceramic capacitors to be reduced to very low values. At very low values of ESR, however, the output voltage's ripple shape changes from triangular to a non-linear shape (e.g., parabolic and sinusoidal). This causes the output voltage to overshoot the hysteretic threshold, and results in higher peak-to-peak ripple. As a result, the very improvements that were intended to lower the output voltage ripple in DC—DC converters can actually cause increased ripple when used in a ripple regulator.
SUMMARY OF THE INVENTION
In accordance with the present invention, shortcomings of conventional ripple regulators, including those described above, are effectively obviated by means of a synthetic ripple regulator, which is operative to generate an auxiliary voltage waveform, such as one that effectively replicates or mirrors the waveform ripple current through the output inductor, and uses this auxiliary voltage waveform to control toggling of the hysteretic comparator. Using such a reconstructed current for ripple regulation results in low output ripple, input voltage feed forward, and simplified compensation.
The auxiliary voltage waveform may be readily generated by coupling the voltage across the inductor to a transconductance amplifier, the output of which feeds a ‘ripple voltage’ capacitor with a ramp current that is proportional to the voltage across the inductor. Since the voltage across a current-driven capacitor is equivalent to the current through a voltage-driven inductor, driving the ripple capacitor with a current proportional to the voltage across the inductor provides the desired waveform shape for controlling the hysteresis comparator. For a step input voltage change, the ramp current will change proportionally, to modify the conduction interval of the power switching devices.
An error amplifier is inserted upstream of the hysteresis comparator and is coupled to receive the regulating reference voltage. The error amplifier serves to increase DC regulation accuracy, providing high DC gain to reduce errors due to ripple wave shape, various offsets, and other errors. The output of the error amplifier follows the load current and is fed to the reference input of the hysteresis comparator.


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patent: 4413224 (1983-11-01), Krupka et al.
patent: 4521726 (1985-06-01), Budnik
patent: 4658204 (1987-04-01), Goodwin
patent: 5399958 (1995-03-01), Iyoda
patent: 6147478 (2000-11-01), Skelton et al.
patent: 6433525 (2002-08-01), Muratov et al.
patent: 6583610 (2003-06-01), Groom et al.
patent: 3343883 (1984-06-01), None
patent: 4206478 (1993-09-01), None
patent: 0650250 (1994

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