Static information storage and retrieval – Read only systems
Reexamination Certificate
2002-08-26
2004-09-14
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Read only systems
C365S189090
Reexamination Certificate
active
06791858
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to CMOS imaging devices, and more specifically, to controlling current supplied to analog circuitry of the CMOS imager.
2. Brief Description of the Related Art
Power reduction in CMOS imaging devices is an important design consideration, especially for devices targeted at handheld applications. Generally, analog power consumption is proportional to the master current of each CMOS imager chip. Analog power consumption is primarily the sum of the bias currents of each of the analog circuits. These bias currents are proportional to the master current, generated by the master current reference.
Unfortunately, this master current will vary quite significantly from chip to chip due to process (and other) variations. To ensure correct operation for all of the analog circuits on all chips without a significant yield loss, the master current reference must be designed to provide a minimum value that is three standard deviations above the distribution of master currents for CMOS chips being produced. With typical variations, this means that the average master current must often be designed to be at least 10% to 15% above the minimum required value.
Operating the master current reference so that a higher current is produced requires additional power. It would be preferable to avoid having to supply higher currents so that the CMOS imaging devices could operate at lower power requirements.
BRIEF SUMMARY OF THE INVENION
The present invention mitigates the disadvantages of the prior art by providing a programmable current multiplication stage between a master current reference and the analog circuitry. The value of master current of each chip can be stored on-chip, for example, with laser fusing in a production testing stage. By programming the current multiplication stage using the stored master current information, the master current can be chosen to be the correct value for each chip, regardless of variations in manufacturing, thereby advantageously improving the production specification to the customer.
During production test, the master current is measured by a mixed signal tester. The tester then calculates the value required to be programmed into the multiplication stage and burns this into a dummy pixel row. Once the sensor has been tested a read only memory which may conveniently be programmed with information is read at the beginning of each frame and loaded into the current multiplier at the beginning of each frame.
The programmed master current will then be accurate from chip to chip (within the accuracy of the multiplication stage), without the need for over-designing the master current reference to handle a wide range of possible current requirements. This will allow the current consumption of the CMOS imager to be reduced from the 10% to 15% higher value that is used in prior art systems to compensate for chip to chip master current variations.
REFERENCES:
patent: 2002/0074481 (2002-06-01), McGrath et al.
patent: 2003/0076432 (2003-04-01), Luo et al.
Barna Sandor L.
Rossi Giuseppe
Dickstein , Shapiro, Morin & Oshinsky, LLP
Le Thong Q.
Micro)n Technology, Inc.
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