Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-05-17
2004-10-05
Nebling, John (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S016000
Reexamination Certificate
active
06800494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device manufacturing and, more particularly, to a method and apparatus for controlling copper barrier/seed deposition processes.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Generally, a set of processing steps is performed on a group of wafers, sometimes referred to as a “lot,” using a variety of processing tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc. The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can create non-optimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
One technique for improving the operation of a semiconductor processing line includes using a factory wide control system to automatically control the operation of the various processing tools. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface which facilitates communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates-a control script based upon a manufacturing model, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. Often, semiconductor devices are staged through multiple manufacturing tools for multiple processes, generating data relating to the quality of the processed semiconductor devices.
During the fabrication process various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process steps result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device. In modern semiconductor devices, copper is increasingly becoming the material of choice for forming conductive interconnections on an integrated circuit device. This is due, in large part, to the enhanced electrical characteristics of copper as compared to other materials, e.g., aluminum, previously used to form such interconnections. Because copper is not readily etched by chemical means, various techniques, such as single damascene and dual damascene, have been employed in forming conductive interconnections comprised of copper. In general, such processes involve forming a patterned layer of insulating material having multiple openings, such as trench interconnect lines or interconnect vias, formed therein, forming a barrier metal layer above the patterned insulating layer and in the openings, forming a copper seed layer above the barrier metal layer, performing an electroplating process to deposit a bulk copper layer above the copper seed layer and, thereafter, performing one or more chemical mechanical polishing processes to remove the excess copper and barrier material from above the patterned insulating layer.
During this process of forming copper conductive interconnections, variations in the thickness of the barrier metal layer and/or the copper seed layer may cause variations in the thickness of the bulk copper layer deposited by the electroplating process. That is, the bulk copper layer may be, for example, thicker in a center region of a wafer than at an edge region of the wafer. In turn, such variations may be problematic with respect to the chemical mechanical polishing processes in that such processes may take more time to complete, and/or may result in uneven removal, dishing and/or erosion of the bulk copper layer.
Additionally, the processes used to form the barrier metal layer and the copper seed layer are very complex and involve many variables that may impact the quality of the resulting barrier metal layer and/or copper seed layer. Typically, the barrier metal layer and copper seed layer are formed by performing a known “recipe” in the appropriate process tool. However, for a variety of reasons, the parameters of the recipe, e.g., DC/RF power, gas flow rates, pressure, voltage levels, DC bias, temperature (both heating and cooling), etc., tend to drift during the course of manufacturing multiple lots of wafers. Such process variations, albeit relatively small in magnitude, may adversely impact the ability to produce barrier metal layers and copper seed layers of the desired quality and consistency such that the processes used to form the copper interconnections in modem integrated circuit devices are not adversely impacted.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
The present invention is generally directed to various methods of controlling copper barrier/seed deposition processes, and a system for accomplishing same. In one illustrative embodiment, the method comprises performing at least one process operation to form a barrier metal layer and a copper seed layer above a wafer, sensing at least one parameter of at least one process operation and determining an acceptability metric for the barrier metal layer and the copper seed layer based upon the sensed parameter. In some embodiments, the method further comprises modifying at least one parameter of the process operation to be performed to form a barrier metal layer and a copper seed layer on a subsequently processed wafer based upon the determined acceptability metric. In some embodiments, the method further comprises identifying a wafer as unacceptable if the acceptability metric falls below a preselected level. In some embodiments, the acceptability metric may be determined by accessing a model that correlates the sensed parameter(s) to an acceptability metric for the barrier metal layer and the copper seed layer.
The present invention is also directed to a system that may be used to form a barrier metal layer/copper seed layer. In one embodiment, the system is comprised of a process tool that is adapted to perform at leas
Brennan William S.
Castle Howard Ernest
Advanced Micro Devices , Inc.
Luk Olivia T.
Nebling John
Williams Morgan & Amerson P.C.
LandOfFree
Method and apparatus for controlling copper barrier/seed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for controlling copper barrier/seed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for controlling copper barrier/seed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3264896