Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-08-07
2004-04-27
Eckert, George (Department: 2815)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S003000, C438S240000, C257S295000, C257S310000
Reexamination Certificate
active
06727156
ABSTRACT:
This application relies for Priority upon Korean Patent Application No.2000-49623, filed on Aug. 25, 2000, the contents of which are the herein incorporated by the reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a ferroelectric capacitor having an improved retention property and manufacturing method thereof.
2. Description of the Related Art
A semiconductor device including a ferroelectric capacitor such as a ferroelectric random access memory (FRAM) device enables high-speed read and write operations with a polarization inversion characteristic and remnant polarization of a ferroelectric layer.
With the polarization inversion of a ferroelectric layer resulting from rotation of dipoles, the FRAM device is known to have operational speed of 10
4
to 10
6
times faster than other non-volatile memory devices such as electrically erasable programmable read-only memory (EEPROM) or flash memory devices. Furthermore, by miniaturization and optimum design concept introduced into the FRAM device, it is known that the FRAM device can obtain write operation speed in hundreds to tens of nanoseconds (ns), thereby allowing for high-speed operation comparable to dynamic random access memory (DRAM). The FRAM device typically requires 2-5 V for polarization inversion, and thus lower voltage single power operation is possible compared to the EEPROM or flash memory requiring a high voltage of 18-22V for a write operation.
The characteristics of the FRAM device is significantly affected by the characteristics of a ferroelectric capacitor. The ferroelectric capacitor characteristics are in turn significantly influenced by the structure of a ferroelectric layer and an electrode used in the capacitor.
The ferroelectric thin films are largely classified into SrBi2Ta2O9 (SBT) films and Pb(Zr1−xTix)O3 (PZT) films. The SBT films having a relatively small remnant polarization value Pr, i.e. 5-10 C/cm
2
, is not ideal for the cell structure of one-Transistor and one-Capacitor (“1T1C”) typically required in a memory device.
Furthermore, the deposition temperature of the SBT films is about 800-850° C. The characteristics of Complementary Metal-Oxide-Semiconductor (CMOS) underlying the SBT film may be affected by such high deposition temperature.
On the other hand, the PZT films are known to be suitable for the cell structure of 1T1C for a highly integrated ferroelectric memory device because they have a relatively large remnant polarization value Pr, i.e. greater than 30 &mgr;C/cm2 (S. Y. LEE, 1999, “A FRAM Technology Using 1T1C and Triple Metal Layer for High Performance and High Density FRAMs”, Symposium on VLSI Technology Digest of Technical Papers, p141). Furthermore, because the deposition temperature is 600-700° C., the characteristics of the CMOS integrated under the PZT film are relatively less affected by the deposition temperature. Thus, effort has been recently made to actively apply the PZT film to ultra highly integrated ferroelectric memory devices made (R. Ramesh et al., Mar. 21, 1994, “Scaling of Ferroelectric Properties in La—Sr—Co—O/Pb—La—Zr—Ti—O/La—Sr—Co—O Capacitors', Appl. Phys. Lett., Vol. 64, No. 12).
Two main properties that ferroelectric capacitors are desirable to have as a non-volatile memory device may be endurance property and retention property. The endurance property refers to resistance against data destruction due to repetitions of read/write operations, and the retention property refers to how long stored data can be retained. In order to improve the retention property, use of a metal oxide electrode as a capacitor electrode in adopting PZT to a capacitor is proposed (H. N. Al-Shareef et al., Mar. 1, 1995, “Electrical Properties of Ferroelectric Thin Film Capacitors with Hybride (Pt, RuO2) for Nonvolatile Memory Applications”, J. Appl. Phys., 77(5), pp. 2146-2154; Takashi Nakamura et al., 1994, “Preparation of Pb(Zr,Ti)O3 Thin Film on Ir and IrO2 Electrodes”, Jpn. J. Appl. Phys. Vol. 33, 1994, Pt1. No. 9B, pp. 5207-5210).
However, with the metal oxide electrode as capacitor electrode significant improvement in the retention property and preventing degradation in the endurance property at the same time are difficult to attain. This is because a high density of interface defects may be caused by instability at the interface between the metal oxide electrode and the PZT film. Thus a large quantity of space charges may occur at the interface. This could result in the compensation and reduction of non-volatile remnant polarization induced by dipole, and eventually may degrade the retention property.
Furthermore, the metal oxide electrode is difficult to be implemented in a capacitor over bit line (COB) structure. In line with a current tendency of using the COB structure for high integration and large storage capacity of a semiconductor device, attempts to adopt the COB structure is made in FRAM devices. However, with the metal oxide electrode, an undesired oxide layer can be formed between a conductive plug for electrically connecting a lower electrode of a capacitor with underlying active region of a semiconductor substrate, and the lower electrode. The undesired oxide layer may degrade the characteristics of a capacitor.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a semiconductor device having a ferroelectric capacitor capable of improving endurance and retention properties, and manufacturing method thereof.
Accordingly, to accomplish the above objective, the present invention provides a method of manufacturing a semiconductor device having a ferroelectric capacitor in which upper and lower electrodes have a triple layered structure of metal layer/metal oxide layer/metal layer. Specifically, a conductive plug electrically connected to a semiconductor substrate is formed by penetrating through an insulating layer on the semiconductor substrate. A first lower metal layer that is electrically connected to the conductive plug and prevents diffusion of oxygen into the conductive plug is formed on the insulating layer. A conductive lower metal oxide layer is formed on the first lower metal layer. A second lower metal layer for inducing interface lattice matching is formed on top of the lower metal oxide layer to form a lower electrode layer comprised of the first lower metal layer, the lower metal oxide layer, and the second lower metal layer.
A ferroelectric layer is formed on the lower electrode layer, and a first upper metal layer for inducing interface lattice matching is formed on top of the ferroelectric layer formed of a ferroelectric material. After having formed the first upper metal layer, a heat treatment is performed above the crystallization temperature of the ferroelectric material to induce interface lattice matching at the interfaces between the first upper metal layer and the ferroelectric layer, and between the second lower metal layer and the ferroelectric layer. A conductive upper metal oxide layer is formed on top of the first upper metal layer. A second upper metal layer for preventing diffusion of a material on top of the upper metal oxide layer is formed on the upper metal oxide layer to form an upper electrode layer comprised of the first upper metal layer, the upper metal oxide layer, and the second upper metal layer. After forming an upper insulating layer on top of the upper electrode layer, the upper insulating layer is penetrated to form a wire electrically connected to the upper electrode layer.
Here, an adhesive layer formed of a titanium layer underlies the first lower metal layer. The first lower metal layer and the second upper metal layer are preferably formed of iridium, and the lower metal oxide layer and the upper metal oxide layer are preferably formed of iridium oxide. The second lower metal layer and the first upper metal layer are preferably formed of platinum, and the ferroelectric layer is preferably formed of Pb(
Jung Dong-jin
Kim Ki-nam
Diaz José R.
Eckert George
Marger & Johnson & McCollom, P.C.
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