Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-10-10
2004-04-06
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185330
Reexamination Certificate
active
06717852
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-314163, filed Oct. 11, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrically erasable/rewritable nonvolatile semiconductor memory device (EEPROM) and more specifically to a semiconductor memory having a plurality of banks and adapted to, while performing a write or erase operation (hereinafter referred to as a write/erase operation) on a bank, allow another bank to be read from. That is, the present invention relates to a semiconductor memory (flash memory) which can perform a write/erase operation and a read operation at the same time and allows for batch erasing.
2. Description of the Related Art
In recent flash memories, in order to reduce the number of memory chips required for a system, a proposal has been made of a memory system, called RWW (Read While Write), which, while reading from a certain memory area, permits a write/erase operation to be performed on another memory area.
The same assignee as this application has proposed in Japanese Patent Application No. 2000-127106 a flash memory which allows concurrent execution of a write/erase operation and a read operation.
In such a flash memory, unless a bank to be written/erased and a bank to be read are completely electrically isolated from each other, multiple selection will occur between the banks, which may result in failure of data reading to be performed correctly.
In the semiconductor memory device proposed in the above Japanese Patent Application, it is important to prevent the multiple selection of a bank to be written/erased and a bank to be read while a write/erase operation and a read operation are performed concurrently.
A semiconductor memory device according to an aspect of the present invention allows, by timing properly the control signals at the start of a write/erase operation, a bank in a write/erase operation and a bank in a read operation to be isolated completely from each other so that they do not interfere with each other and multiple selection of a write/erase execution bank and a read execution bank to be prevented surely. Therefore, a write/erase operation and a read operation can be executed normally and concurrently.
A semiconductor memory device according to another aspect of the present invention allows, by timing properly the control signals at the end of a write/erase operation, a bank in a write/erase operation and a bank in a read operation to be isolated completely from each other so that they do not interfere with each other and multiple selection of a write/erase execution bank and a read execution bank to be prevented surely. Therefore, a write/erase operation and a read operation can be executed normally and concurrently.
A semiconductor memory device according to an aspect of the present invention allows, by timing properly the control signals at the suspending or resuming of a write/erase operation, a bank in a write/erase operation and a bank in a read operation to be isolated completely from each other so that they do not interfere with each other and multiple selection of a write/erase execution bank and a read execution bank to be prevented surely. Therefore, a write/erase operation and a read operation can be executed normally and concurrently.
BRIEF SUMMARY OF THE INVENTION
A first semiconductor memory device according to an embodiment of the present invention comprises: a memory cell array having electrically rewritable nonvolatile memory cells and divided into a plurality of cores each of which is composed of one or more blocks each comprised of a range of memory cells as a unit of data erasure; a core select circuit selecting an arbitrary number of cores from the plurality of cores for data writing/erasing; a data write circuit writing data into selected memory cells in a core selected by the core select circuit; a data erase circuit erasing data in a selected block in a core selected by the core select circuit; and a data read circuit reading data from memory cells in a core which is not selected by the core select circuit, the sequence in which, at the start of a write/erase operation, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.
In a second semiconductor memory device according to an embodiment, the sequence in which, at the end of a write/erase operation, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are reset being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.
In a third semiconductor memory device according to an embodiment, the sequence in which, at the suspending of a write/erase operation, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are reset being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.
In a fourth semiconductor memory device according to an embodiment, the sequence in which, at the resuming of a write/erase operation which has been suspended, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.
A fifth semiconductor memory device according to an embodiment of the present invention is configured so as to satisfy the four sequential relationships among the control signals at the start, end, suspending and resuming of a write/erase operation in the above first through fourth semiconductor memory devices.
REFERENCES:
patent: 5841696 (1998-11-01), Chen et al.
patent: 6208556 (2001-03-01), Akaogi et al.
patent: 6243313 (2001-06-01), Sakamoto et al.
patent: 6377502 (2002-04-01), Honda et al.
patent: 1 052 647 (2000-11-01), None
patent: 2001-325795 (2001-11-01), None
Pub. No.: US 2002/0031038 A1; Appl. No.: 09/987,981; Filed: Nov. 16, 2001; Inventors: Yasuhiko Honda et al.
Hara Tokumasa
Honda Yasuhiko
Kato Hideo
Kuriyama Masao
Saito Hidetoshi
LandOfFree
Nonvolatile semiconductor memory device capable of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory device capable of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device capable of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3263373