Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-09-16
2004-10-19
Nguyen, Van Thu (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S370000, C257S378000, C257S401000, C257S499000, C257S517000, C257S565000
Reexamination Certificate
active
06806550
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an evaluation configuration for a semiconductor memory. Such an evaluation configuration contains, in particular, a first MOS evaluation stage of a first conductivity type with cross-coupled first and second MOS transistors of the first conductivity type, which are connected, by their source-drain paths, in parallel with one another and in series with a third MOS transistor of the first conductivity type. The third MOS transistor is clocked with a first voltage and to which a supply potential is applied.
A preferred semiconductor memory is a dynamic random access memory (DRAM). As is known, a DRAM cell contains a capacitance, in which the cell content is stored, and a MOS selection or isolation transistor. So-called evaluation configurations or sense amplifiers are used to evaluate a read signal read from the capacitance. They are regularly embodied using CMOS technology.
An ideal evaluation configuration should be able to evaluate positive and negative differential signals with arbitrarily small magnitude, provided that the entire circuit configuration of the DRAM including bit lines and reference lines is completely symmetrical. In practice, however, in actual fact small differences in the selection transistors and the bit lines always occur which ultimately cause an offset of the evaluation configuration. The consequence of this is that a read signal must be greater than an off set voltage. In order to be able to identify a cell content reliably as a “1” or “0”.
The largest contribution to the offset is supplied by the transistors of the evaluation configuration, this being due to variations from their geometrical dimensions and their electrical parameters. What is problematic, then, is that the variations increase more and more upon the scaling of the transistors. The consequence of this is that the offset voltage of a CMOS evaluation configuration lies between 5 mV and 10 mV and cannot be improved further.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an evaluation configuration for semiconductor memories which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which can reliably detect very small read signals and allows a high integration density.
With the foregoing and other objects in view there is provided, in accordance with the invention, an evaluation configuration for semiconductor memories. The evaluation configuration contains a first MOS evaluation stage, a second bipolar evaluation stage, and an isolation stage connected between the first MOS evaluation stage and the second bipolar evaluation stage. The isolation stage isolates the second bipolar evaluation stage from the first MOS evaluation stage.
The evaluation configuration according to the invention has, in particular, a second bipolar evaluation stage containing cross-coupled first and second bipolar transistors with base zones of the first conductivity type, which are connected, by their drain-emitter paths, in parallel with one another and in series with the third bipolar transistor. The third bipolar transistor is clocked with a second voltage and to which a reference-ground potential is applied. An isolation stage isolates the second evaluation stage from the first evaluation stage and contains fourth and fifth MOS transistors of a second conductivity type, which are interconnected by their gates. The fourth MOS transistor is connected in series with the first MOS transistor and the first bipolar transistor and the fifth MOS transistor is connected in series with the second MOS transistor and second bipolar transistor. In this case, the first conductivity type is preferably a p-conductivity type.
The evaluation configuration according to the invention thus preferably uses npn bipolar transistors. The latter are distinguished by a high sensitivity, a good gain and a high rapidity for, for example, a supply voltage range that is greater than 0.7 V. The evaluation configuration can evaluate very small read signals. In this case, the sensitivity of the evaluation configuration is about 1 mV, which can be attributed to the fact that the offset voltage of npn bipolar transistors, with about 1 mV, is a factor of 5 to 10 smaller than that of MOS transistors. The layout of the evaluation configuration can readily be integrated easily into a cell array. A simulated evaluation operation lasts approximately 7 ns in the case of a supply voltage of about 1.5 V and approximately 14 ns in the case of a supply voltage of 0.7 V.
The evaluation configuration according to the invention can readily be used in DRAMs, SRAMs and flash EPROMs etc. Its essential advantage is that it can evaluate a significantly smaller read signal compared with previous evaluation configurations. The use of the bipolar transistors makes it possible to overcome the relatively high offset voltage of evaluation configurations using CMOS technology.
Ultimately, in the case of the evaluation configuration according to the invention, the very small read signal is first evaluated and amplified by the second bipolar evaluation stage containing preferably npn bipolar transistors and is then brought to the high level again by the first MOS evaluation stage in a subsequent step, when the read signal has already been amplified to a few hundred mV.
This yields significant advantages. With the preferably npn bipolar transistors, the offset voltage can be lowered to about 1 mV, which is a factor of 5 to 10 times lower than in MOS transistors.
A voltage gain a
0
is dependent on the drain-source current I
DS
in the case of MOS transistors, while the voltage gain a
0
is independent of the current and constant in the case of bipolar transistors.
In accordance with an added feature of the invention, the first MOS evaluation stage has a first MOS transistor with a source-drain path and a second MOS transistor with a source drain path. The first MOS transistor is cross-coupled with the second MOS transistor. The source-drain path of the first MOS transistor is disposed in parallel with the source-drain path of the second MOS transistor. A third MOS transistor is disposed in series with the source-drain path of each of the first and second MOS transistors. The third MOS transistor is clocked with a voltage and receives a supply potential.
In accordance with an additional feature of the invention, the first MOS transistor and the second MOS transistor each have a channel of the given (first) conductivity type. The third MOS transistor has a channel of the given (first) conductivity type. The fourth MOS transistor and the fifth MOS transistor have a channel of a further (second) conductivity type.
In accordance with another feature of the invention, the third bipolar transistor has a collector. The first bipolar transistor has a base, a collector, and an emitter connected to the collector of the third bipolar transistor. The second bipolar transistor has a base connected to the collector of the first bipolar transistor, a collector connected to the base of the first bipolar transistor, and an emitter connected to the collector of the third bipolar transistor.
In accordance with a further feature of the invention, there is provided a memory array having a first side and a second side. The first MOS evaluation stage is disposed at the first side of the memory array. The second bipolar evaluation stage and the isolation stage are disposed on the second side of the memory array.
In accordance with a concomitant feature of the invention, the bit lines are connected between the first MOS evaluation stage and the isolation stage.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an evaluation configuration for semiconductor memories, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without depa
Hoffmann Kurt
Kowarik Oskar
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Menz Douglas
Nguyen Van Thu
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