Electricity: conductors and insulators – Feedthrough or bushing – Compression
Reexamination Certificate
2002-01-23
2004-10-05
Tu, Christine T. (Department: 2133)
Electricity: conductors and insulators
Feedthrough or bushing
Compression
C714S744000, C713S400000
Reexamination Certificate
active
06800817
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field and pertains, more specifically, to a semiconductor component for connection to a test system and to a test system having the semiconductor component.
In order to provide functional tests in semiconductor chips, for example mass memory chips, it is customary to integrate self-test circuits in the chip (BIST, Built In Self Test).
In a test environment, a test device connected to the chip to be tested (DUT, Device Under Test) can be used to transmit, via a plurality of connection pads or connection pins, clock signals, data signals, addresses and commands to the chip to be tested. For this purpose, it has been customary heretofore to transmit data, commands and addresses in parallel into the DUT. However, this is associated with the disadvantage that a large number of pins or connection legs are required on the chip in order to be able to carry out self-tests.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor component for connection to a test system and a test system having the semiconductor component, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which the number of connection legs or pins required for carrying out self-tests on the semiconductor component is reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component for connection to a test system, comprising:
at least one connection on the semiconductor component for receiving an external clock signal with a modulated duty ratio;
a clock recovery circuit having an input connected to the at least one connection on the semiconductor component, and an output outputting a periodic clock signal having a frequency of the external clock signal with the modulated duty ratio; and
a shift register having a serial data input connected to the at least one connection on the semiconductor component, and a clock input connected to the output of the clock recovery circuit.
With the above and other objects in view there is also provided, in accordance with the invention, a test system, comprising at least one semiconductor component according to the above summary, and a test device for testing the at least one semiconductor component, the test device having an output connected to the at least one connection of the at least one semiconductor component and carrying the external clock signal with the modulated duty ratio.
The semiconductor component described has, for carrying out self-tests, just one connection leg or pin or connection pad at which the modulated clock signal can be fed in. With this modulated clock signal, on the one hand it is possible to communicate the reference clock required for the test functions and, on the other hand, it is possible to communicate serially data, addresses and commands for a self-test program in the semiconductor component.
In order that the at least one connection on the semiconductor component can be utilized not only for a test mode but also for a normal mode of the semiconductor component, it is possible to provide a changeover switch or multiplexer for coupling shift register input and clock recovery circuit input to the external connection on the semiconductor component, to which, moreover, it is possible to connect a circuit section for carrying out a normal mode in the semiconductor component.
The clock recovery circuit in the semiconductor component enables the recovery of a periodic clock signal from the modulated clock signal. The shift register is driven by this recovered, periodic clock signal at a clock input, with the result that correctly timed sampling of the modulated clock signal, for example with the falling edge of the recovered clock signal, provides demodulation of a data signal from the modulated clock signal in the shift register.
A clock signal is to be understood as a periodic signal, for example a square-wave signal with a symmetrical duty ratio, that is to say a duty cycle of, for example, 50 percent. This means that 50% of the clock period duration of the clock signal is equal to the duration of a high level in the clock signal. The temporal profile of a clock signal is accordingly determined at any arbitrary instant.
A data signal is understood as a signal with a signal profile that is not known a priori. Consequently, a data signal is not usually a periodic signal.
The frequency identity of periodic clock signal and modulated clock signal is understood as the identity of the period durations of the two signals.
The transmission of data, addresses or commands with the modulated clock signal can be effected in packets. In this case, each packet may contain additional information as to whether the information items transmitted in the packet are data, addresses or commands. In the semiconductor component, a decoder which decodes the correspondingly identified packet information items may be provided in a test circuit. With the present semiconductor component, long data sequences, for example different programs for carrying out a BIST, Built In Self Test, can also be loaded into the semiconductor component. Furthermore, costs are saved with the present semiconductor component since only one pin or connection on the semiconductor component has to be contact-connected in a test environment. Moreover, it is thus possible to increase the number of semiconductor components that can be tested simultaneously by a test device through a higher degree of parallelization and to save time and costs. This is advantageous in particular in mass production processes with large numbers, as are customary in chip fabrication.
In accordance with an added feature of the invention, the semiconductor component is a mass memory chip. A test environment that is simple to realize or a test system is particularly advantageous in mass memory chips, for example for checking the memory cells for defects.
In accordance with an additional feature of the invention, the semiconductor component is a DRAM, Dynamic Random Access Memory, with a memory space of greater than or equal to 64 Megabits. However, the semiconductor component may also have a memory space of less than 64 Mbit.
In accordance with another feature of the invention, the periodic clock signal is a square-wave signal with a symmetrical duty ratio of 50%. Duty ratio is also referred to as duty cycle. A duty ratio of 50% means that, within a clock period, the time duration of a logic high level is equal to the time duration of a logic low level is equal to half the period duration of the clock signal. Although a duty ratio of 50% is particularly advantageous, a semiconductor component for operation with a duty ratio other than 50% also lies within the scope of the invention.
In accordance with a further preferred embodiment of the present invention, the shift register is a 4-bit shift register. In this case, under the control of the regenerated clock signal, the 4 bits of memory space of the shift register are read bit by bit serially into the shift register. In a further preferred embodiment of the present invention, the clock input of the shift register is an input which triggers the data input of the shift register in response to the falling edge. This defines in each case periodically recurring evaluation instants with regard to the modulated clock signal at which in each case the modulated clock signal can be sampled and, by this means, in a simple manner, a data signal with which the clock signal is modulated can be recovered.
Depending on the application, significantly larger shift registers than 4-bit shift registers can also advantageously be used, for example when addresses such as row and/or column addresses are to be stored for a memory chip.
In accordance with again an added feature of the invention, the shift register has a parallel data output for parallel read-out of the shift register. This enables parallel further processing of th
Kaiser Robert
Schamberger Florian
Schneider Helmut
Mayback Gregory L.
Tu Christine T.
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