Semiconductor memory and control method

Details Semiconductor memory and control method Semiconductor memory and control method

2003-01-23

2004-03-30

Le, Vu Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S222000, C365S206000

Reexamination Certificate

active

06714479

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device provided with an address transition detection (ATD) circuit for detecting a transition in an externally provided address signal, and more particularly, to a semiconductor memory device and control method composed so as to perform a refresh operation and read/write operation using a pulse signal output from an ATD circuit as a trigger.
BACKGROUND ART
In the past, so-called pseudo SRAM were used as semiconductor memory devices composed so as to be able to be handled in the manner of SRAM (Static Random Access Memory) despite consisting primarily of DRAM (Dynamic Random Access Memory). These pseudo SRAM employ an internal synchronization scheme that operates by detecting a transition in an address signal, and are equipped with an address transition detection circuit (abbreviated as ATD circuit, or address transition detector) for detecting a transition in an externally provided address signal. In the case of this pseudo SRAM, although it is difficult to obtain high-speed performance in the manner of regular SRAM having memory cells comprised of flip-flops since it consists primarily of DRAM, pseudo SRAM are able to realize large-scale storage capacity comparable to DRAM.
FIG. 7
shows an example of the configuration of an address input system of a pseudo SRAM provided with an ATD circuit. Address signals ADD
0
to ADDn (n is a natural number) are address signals applied from the outside. Address input circuits
800
-
0
to
800
-
n
are provided corresponding to these address signals ADD
0
through ADDn, and each of these address input circuits is composed of an input buffer
801
and latch circuit
802
. In addition, ATD circuits
810
-
0
to
810
-
n
are provided for the outputs of each address input circuit, and each of the output signals of these ATD circuits are input to pulse generator
820
.
Here, input buffers
801
of address input circuits
800
-
0
to
800
-
n
receive externally provided address signals (ADD
0
to ADDn), and convert them to internal device address signals. In addition, latch circuits
802
latch address signals output from input buffers
801
based on a control signal output from a prescribed control circuit system not shown in the case an external address signal has changed, and normally, allow the output signals of input buffers
801
to pass through as internal address signals (IA
0
to IAn).
ATD circuits
810
-
0
to
810
-
n
generate positive one-shot pulses &phgr;
0
to &phgr;n by detecting a change (transition) in internal address signals IA
0
to IAn output from latch circuits
802
of address input circuits
800
-
0
to
800
-
n.
Pulse generator
802
receives one-shot pulses &phgr;
0
to &phgr;n output from ATD circuits
810
-
0
to
810
-
n,
and generates a pulse address transition detection signal &phgr;a having a prescribed pulse width. Various types of control signals required for operation of each section are then derivatively generated based on this pulse address transition detection signal &phgr;a.
According to a semiconductor memory device of the background art equipped with this type of address input system, in the case address signals ADD
0
to ADDn provided from the outside are in a steady state without changing, address signals incorporated from the outside through input buffers
801
in each of address input circuits
800
-
0
to
800
-
n
pass through latch circuits
802
in the through state, and are provided to, for example, a pre-decoding circuit of a latter stage as internal address signals IA
0
to IAn. In this state, since there is no change in the address signals, ATD circuits
810
-
0
to
810
-
n
do not generate one-shot pulses &phgr;
0
to &phgr;n, and pulse address transition detection signal &phgr;a is held at the low (L) level.
In
FIG. 7
, if, for example, an externally provided address signal ADD
0
changes from this state, internal address signal IA
0
output from input buffer
801
through latch circuit
802
in the through state changes. ATD circuit
810
-
0
detects this change in address signal IA
0
, and generates one-shot pulse &phgr;
0
. Pulse generator
802
then receives one-shot pulse &phgr;
0
generated with ATD circuit
810
-
0
, and outputs a pulse signal as pulse address transition detection signal &phgr;a.
Similarly, if other externally provided address signals ADD
1
to ADDn change, pulse generator
802
receives a one-shut pulse generated with each ATD circuit, and outputs pulse address transition detection signal &phgr;a. Control signals required for memory cell refresh operation or control signals required for read/write operation are generated in a control signal generation circuit system not shown in the drawings based on this pulse address transition detection signal &phgr;a, and various operations within the device are controlled at the appropriate timing.
However, in the case of the above pseudo SRAM, due to its specifications, a constitution is employed in which both the operations of refresh operation and read/write operation are performed consecutively within the same cycle based on a common pulse address transition detection signal &phgr;a. Consequently, if noise is contained in externally provided address signals ADD
0
to ADDn, one-shut pulses &phgr;
0
to &phgr;n are generated following a malfunction of ATD circuits
810
-
0
to
810
-
n
due to this noise. As a result, the refresh operation and read/write operation are consecutively performed incorrectly, and since the majority of the circuits that compose the semiconductor memory device operate, a large operating current is generated that results in the problem of increased current consumption.
A first example of the background art that attempts to solve problems caused by this type of ATD circuit malfunction is the semiconductor memory device disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 3-12095. This semiconductor memory device is provided with a first address transition detection circuit that generates a pulse signal for controlling the read operation until immediately before an output buffer, and a second address transition detection circuit that generates a pulse signal for controlling operation beyond the output buffer, and a filter is provided in a prior stage of this second address transition detection circuit for removing noise contained in address signals.
According to this device, even if apparent noise is contained in address signals caused by fluctuation in ground potential Vss accompanying operation of the output buffer, this noise is removed by a filter. Thus, the second address transition detection circuit that generates a pulse signal for controlling output buffer operation does not malfunction due to this noise, and malfunction of the output buffer also no longer occurs caused by spontaneously generated ground potential noise. In addition, in this device, since the operation of the circuit system until immediately before the output buffer, which determines the majority of read time, is controlled by a pulse signal from the first address transition detection circuit that inputs address signals without going through a filter, high-speed performance is not impaired. However, this semiconductor memory device according to this first example of the background art prevents malfunctions caused by fluctuation of ground potential Vss accompanying output buffer switching, and in the case the refresh operation and read/write operation are performed within the same cycle, is unable to suppress the generation of operating current caused by noise contained in an address.
In addition, a second example of a device according to the background art is the semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 5-81888. This semiconductor integrated circuit is provided with an ATD circuit (to be referred to as the first ATD circuit) for detecting transitions in address signals, a noise filter for removing noise from addresses, and an ATD circuit (to be referred

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