Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-01-02
2004-09-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S390000, C257SE27026
Reexamination Certificate
active
06787825
ABSTRACT:
The present invention concerns a data storage and data-processing apparatus, as well as a method for fabricating the same.
The invention particularly concerns a data storage and data-processing apparatus 3D scalable single- and multilayer memory and data-processing modules and apparatus; and which even more particularly are based on ROM and/or WORM and/or REWRITABLE blocks addressed in a passive matrix scheme.
The present application claims priority from Norwegian Patent Application No. 982518 titled “Scalable integrated data-processing device”, which has been assigned to the Assignee of the present invention and the disclosure of which is hereby additionally incorporated by reference. This scalable integrated data-processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data-processing device is provided on a carrier substrate and comprises mutually adjacent, substantially parallel layers stacked upon each other. The processing unit and the storage unit are each provided in one or more such layers and/or in layers formed with a selected number of processors and memories in selected combinations.
In each layer are provided horizontal electrical conducting structures which constitute internal electrical connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. These further electrical structures in a layer are provided on at least a side edge of the layer as electrical edge connections and/or preferably as vertical conducting structures which form an electrical connection in a cross-direction of the layer and perpendicular to its plane to contact electrical conducting structures in other layers.
In particular, the layers may be formed of a plurality of sublayers made of organic thin-film materials. Some of all layers or sublayers may also be made with organic or inorganic thin-film materials or both.
A preferred embodiment of the data-processing device according to the priority application is shown in FIG.
1
. Advantageously are here processors and memories, the latter, e.g., RAMs assigned to the processors, provided in one and the same layer. A processor interface
3
with an I/O interface
8
is provided on a substrate S and above the processor interface
3
follows a processor layer P
1
with one or more processors. Both the processor interface
3
and the processor layer P
1
may as the lowermost layers in the data-processing device and adjacent to the substrate be realized in conventional, e.g., silicon-based technologies.
Above the processor layer P
1
is provided a first memory layer M
1
which may be configured with one or more RAMs
6
assigned to the processors
5
in the underlying processor layer P
1
. In
FIG. 1
, however, the separate RAMs
6
in the memory layer M
1
are emphasized in particular. On the other hand it is shown how the memories in the memory layer M
1
may be directly connected to the underlying processor layer P
1
via buses
7
, the stacked configuration allowing such buses
7
to be provided in a large number by being realized as vertical conducting structures, while the configuration layer-on-layer allows for a large number of such bus connections being provided between the processor layer P
1
and the memory layer M
1
and in addition with short signal paths. It will be realized that the juxtaposed arrangement in a surface would in contrast require longer connections and consequently longer transfer times.
Further, the data-processing device as shown comprises combined memory and processor layers MP
1
, MP
2
, MP
3
provided with processors that are connected mutually and to the processor interface
3
via the same processor bus
4
. All the combines memory and processor layers MP comprises one or more processors
5
and one or more RAMs
6
. Above the combined memory and processor layers MP there is provided a memory interface
1
with an I/O interface
9
to external units and above the memory interface
1
follows memory layers M
2
, M
3
, . . . in as large number as desirable and possibly realized as the mass memory of the data-processing device. These memory layers, M
2
, M
3
, etc. are in their turn connected to the memory interface
1
via memory buses realized as vertical conducting structures
2
through the layers M
2
, M
3
, . . . .
The integrated data-processing device has a scalable architecture, such that, in principle, the device can be configured with an almost unlimited processor and memory capacity. In particular, the data-processing device can be implemented in various forms of scalable parallel architectures integrated with optimal interconnectivity in three dimensions.
In addition to comprising random accessible memories, the storage unit of the data-processing device can also comprise memories in the form of ROM, WORM or REWRITEABLE or combinations thereof.
The present invention particularly discloses how the three-dimensional scalable single- and multilayer memory and data-processing modules may be implemented with architectures and processing methods making them suitable for application in a scalable integrated data-processing device of the above-mentioned kind, but not necessarily limited thereto.
BACKGROUND OF THE INVENTION
Advanced DRAM demonstration dies are presently available in 1-gigabit (Gbit) modules based on a 0.18 &mgr;m process over a 570 mm
2
chip area. The conventional one-transistor DRAM cell requires roughly 10&lgr;
2
area (where &lgr; is the minimum feature size) although processing “tricks” can reduce this significantly (40%). However row and column decode, drivers, sense amplifiers, and error correction logic cannot share the same silicon area and account for a significant fraction of the DRAM die area. More importantly, existing DRAM designs to date have not proven scalable to a 3D stacked architecture. By their design, high density DRAM's are also inappropriate as ROM memories. The conventional NOR-gate based ROM requires a nominal cell of 70&lgr;
2
(though again reduced by processing tricks) limiting densities to <10
8
bits/cm
2
under even the most aggressive lithography assumptions. Higher densities can only be achieved through the use of both dense metal designs (minimum metal pitch) coupled with 3D integration. Technically and commercially viable devices of this type have as yet not been forthcoming, although the enormous commercial potential has prompted a great deal of R&D efforts by the electronics industry, which in term has spawned a voluminous patent literature.
3D Data Storage
Stacking of thin layers of memory on top of each other to achieve high volumetric and areal densities has been attempted by using e.g. lift-off techniques for inorganic thin film circuitry. However, the background art has led to designs that have proven too complicated or costly to have a commercial impact. In U.S. Pat. No. 5,375,085 “Three dimensional ferroelectric integrated circuit without insulation layer between memory layers”, B. E. Gnade et al. have disclosed a layered, passively addressed memory stack based on a ferroelectric memory substance. However, no concrete information is given, in particular relating to processability in multiple levels, showing how complete memory devices can be made that include all the required ancillary active circuitry. Several patent applications involving stacking of thin film memory layers etc. and which are of relevance for the present invention, have been filed by the present applicant. These include Norwegian patent applications NO 973993, NO 980781, the above-mentioned NO 982518, NO 980602 and NO 990867.
Dense Metal Designs
Passive matrix addressing provides a density corresponding to a unit cell area of approximately 4&lgr;
2
.
A number of patents exist where ROM devices employ passive matrix addressing schemes, e.g.: U.S. Pat. No. 4,099,260 of D. N. Lynes et al.: “Bipolar read-only-memory unit having self-isolating b
Carlsson Johan
Gudesen Hans Gude
Gustafsson Göran
Leistad Geirr I.
Nordal Per-Erik
Ho Tu-Tu
Nelms David
Thin Film Electronics ASA
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